參數(shù)資料
型號: ST72124J2T
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 139/153頁
文件大?。?/td> 1533K
代理商: ST72124J2T
ST72334J/N, ST72314J/N, ST72124J
139/153
8-BIT ADC CHARACTERISTICS
(Cont’d)
ADC Accuracy
Figure 99. ADC Accuracy Characteristics
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I
=0.8mA, the typical leakage induced inside the die is 1.6μA and the effect on the ADC accuracy is a loss of 1 LSB
for each 10K
increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V
DD
supply, and worst case temperature.
2. Data based on characterization results with T
A
=25°C.
3. Data based on characterization results over the whole temperature range.
Symbol
Parameter
V
DD
=5V,
2)
f
CPU
=1MHz
Typ.
V
DD
=5.0V,
3)
f
CPU
=8MHz
Typ.
V
DD
=3.3V,
3)
f
CPU
=8MHz
Typ
Unit
Max
2.0
1.5
1.5
1.5
1.5
Max
2.0
1.5
1.5
1.5
1.5
Max
2.0
1.5
1.5
1.5
1.5
|E
T
|
E
O
E
G
|E
D
|
|E
L
|
Total unadjusted error
1)
Offset error
1)
Gain Error
1)
Differential linearity error
1)
Integral linearity error
1)
LSB
E
O
E
G
1 LSB
IDEAL
1LSBIDEAL
VDDA
VSSA
256
=
V
in
(LSB
IDEAL
)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
=Offset Error: deviation between the first actual
transition and the first ideal one.
E
=Gain Error: deviation between the last ideal
transition and the last actual one.
E
=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Result ADCDR
255
254
253
5
4
3
2
1
0
V
SSA
7
6
1
2
3
4
5
6
7
253 254 255 256
(1)
(2)
E
T
E
D
E
L
(3)
V
DDA
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