參數資料
型號： ST72124J2T
廠商： 意法半導體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述： 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器
文件頁數： 131/153頁
文件大?。?/td> 1533K
代理商： ST72124J2T
ST72334J/N, ST72314J/N, ST72124J
131/153
16.9 CONTROL PIN CHARACTERISTICS
16.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Figure 90. Typical Application with RESET pin
8)
Notes:
1.
Unless otherwise specified, typical data are based on T
A
=25°C and V
DD
=5V.
2. Data based on characterization results, not tested in production.
3.
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I
current sunk must always respect the absolute maximum rating specified in
Section 16.2.2
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
5. The R
ON
pull-up equivalent resistor is based on a resistive transistor (corresponding I
current characteristics de-
scribed in
Figure 91
). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t
h(RSTL)in
can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Symbol
V
IL
V
IH
V
hys
Parameter
Conditions
Min
Typ
1)
Max
0.3xV
DD
Unit
Input low level voltage
2)
Input high level voltage
2)
Schmitt trigger voltage hysteresis
3)
Output low level voltage
4)
(see
Figure 92
,
Figure 93
)
V
0.7xV
DD
400
0.68
0.28
40
100
6
30
mV
V
OL
V
DD
=5V
I
IO
=+5mA
I
IO
=+2mA
V
DD
=5V
V
DD
=3.4V
0.95
0.45
60
120
V
R
ON
Weak pull-up equivalent resistor
5)
V
IN
=
V
SS
20
80
k
t
w(RSTL)out
Generated reset pulse duration
External pin or
internal reset sources
1/f
SFOSC
μ
s
μ
s
ns
t
h(RSTL)in
t
g(RSTL)in
External reset pulse hold time
6)
Filtered glitch duration
7)
20
100
RESET
V
DD
WATCHDOG RESET
ST72XXX
LVD RESET
INTERNAL
RESET CONTROL
R
ON
0.1
μ
F
V
DD
0.1
μ
F
V
DD
4.7k
EXTERNAL
RESET
CIRCUIT
8)
OPTONAL
USER
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相關代理商/技術參數
參數描述
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ST72124J2T1/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T3/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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