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參數(shù)資料
| 型號： | ST72124J2T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| 中文描述： | 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器 |
| 文件頁數(shù)： | 38/153頁 |
| 文件大?。?/td> | 1533K |
| 代理商： | ST72124J2T |
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ST72334J/N, ST72314J/N, ST72124J
38/153
POWER SAVING MODES
(Cont’d)
11.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see
Section 14.2 "MAIN CLOCK CON-
TROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)" on page 52
for more details on the
MCCSR register).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Table 5, “Interrupt
mapping,” on page 34
) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
Figure 25
).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 18.1 on page 144
for more details).
Figure 24. HALT Timing Overview
Figure 25. HALT Mode Flow-chart
Notes:
1.
WDGHALT is an option bit. See option byte sec-
tion for more details.
2.
Peripheral clocked with an external clock source
can still be active.
3.
Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
Table 5, “Interrupt mapping,” on page 34
for
more details.
4.
Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
HALT
RUN
RUN
4096 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=0]
FETCH
VECTOR
HALT
INSTRUCTION
(MCCSR.OIE=0)
RESET
INTERRUPT
3)
Y
N
N
Y
CPU
I BIT
OSCILLATOR
PERIPHERALS
2)
OFF
OFF
OFF
0
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I BIT
OSCILLATOR
PERIPHERALS
ON
OFF
ON
X
4)
CPU
I BITS
OSCILLATOR
PERIPHERALS
ON
ON
ON
X
4)
4096 CPU CLOCK CYCLE
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT
1)
0
WATCHDOG
RESET
1
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| ST72124J2T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
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| ST72124J2T3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T3/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
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