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ST10F252M
CAN modules
The BSP translates messages into frames and vice versa. It generates and discards the
enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC
code, performs the error management, and decides which type of synchronization is to be
used. It is evaluated at the sample point and processes the sampled bus input bit. The time
after the sample point that is needed to calculate the next bit to be sent (for example, data
bit, CRC bit, stuff bit, error flag, or idle) is called the information processing time (IPT).
The IPT is application specific but may not be longer than 2 tq; the C-CAN’s IPT is 0 tq. Its
length is the lower limit of the programmed length of Phase_Seg2. For a synchronization,
Phase_Seg2 may be shortened to a value less than IPT, which does not affect bus timing.
Calculation of the bit timing parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.
The resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta, the length of the time quantum tq is defined
by the baud rate prescaler with tq = (Baud Rate Prescaler)/fsys. Several combinations may
lead to the desired bit time, allowing iterations of the following steps.
The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay
times measured in the system. A maximum bus length as well as a maximum node delay
has to be defined for expandible CAN bus systems. The resulting time for Prop_Seg is
converted into time quanta (rounded up to the nearest integer multiple of tq).
The Sync_Seg is 1 tq long (fixed), leaving (bit time – Prop_Seg – 1) tq for the two phase
buffer segments. If the number of remaining tq is even, the phase buffer segments have the
same length, Phase_Seg2
= Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 must be considered as well. Phase_Seg2 may
not be shorter than the CAN controller’s information processing time, which is, depending on
the actual implementation, in the range of [0...2] tq.
The length of the synchronization jump width is set to its maximum value, which is the
minimum of four and Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the
If more than one configuration is possible, that configuration allowing the highest oscillator
tolerance range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same
bit rate. The calculation of the propagation time in the CAN network, based on the nodes
with the longest delay times, is done once for the whole network.
The CAN system’s oscillator tolerance range is limited by that node with the lowest tolerance
range.
The calculation may show that bus length or bit rate have to be decreased or that the
oscillator frequencies’ stability has to be increased in order to find a protocol compliant
configuration of the CAN bit timing.
The resulting configuration is written into the bit timing register:
(Phase_Seg2 - 1) and (Phase_Seg1 + Prop_Seg - 1) and (SynchronisationJumpWidth - 1)
and (Prescaler - 1).