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System reset
ST10F252M
20.2
Asynchronous reset
An asynchronous reset is triggered when RSTIN pin is pulled low while the RPD pin is low.
The ST10F252M is immediately (after the input filter delay) forced in reset default state. It
pulls low the RSTOUT pin, it cancels pending internal hold states if any, it aborts all
internal/external bus cycles, it switches buses (data, address and control signals) and I/O
pin drivers to high-impedance, it pulls high PORT0 pins.
Note:
If an asynchronous reset occurs during a read or write phase in internal memories, the
content of the memory itself could be corrupted. To avoid this, synchronous reset use is
strongly recommended.
Power-on reset
Asynchronous reset must be used during the power-on of the device. Depending on crystal
or resonator frequency, the on-chip oscillator needs about 1 ms to 10 ms to stabilize (refer to
Section 27.8.2), with an already stable VDD. The logic of the ST10F252M does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on
conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be
held at low level until the device clock signal is stabilized and the system configuration value
on PORT0 is settled.
At power-on it is important to consider some additional constraints introduced by the
start-up phase of the different embedded modules.
In particular the on-chip voltage regulator needs at least 1 ms to stabilize the internal 1.8 V
for the core logic – this time is computed from when the external reference (VDD) becomes
stable (inside specification range, that is at least 4.5 V). This is a constraint for the
application hardware (external voltage regulator). The RSTIN pin assertion should be
extended to guarantee the voltage regulator stabilization.
A second constraint is imposed by the embedded Flash. When booting from internal
memory, starting from the release of RSTIN, it needs a maximum of 1 ms for its initialization;
before that, the internal reset (RST signal) is not released, so the CPU does not start code
execution in internal memory.
Note:
This is not true if external memory is used (pin EA held low during reset phase). In this case,
once RSTIN pin is released, and after few CPU clock pulses (filter delay plus 3...8 TCL), the
internal reset signal RST is released, so the code execution can start immediately. Access
to the data in internal Flash is forbidden before its initialization phase is completed; an
attempted access during the start-up phase returns FFFFh (just at the beginning), while
later 009Bh (an illegal opcode trap is generated).
At power-on, the RSTIN pin is tied low for a minimum time that includes also the start-up
time of the main oscillator (tSTUP = 1 ms for resonator, 10 ms for crystal) and PLL
synchronization time (tPSUP = 200 s). This means that, if the internal Flash is used, the
RSTIN pin could be released before the main oscillator and PLL are stable to recover some
time in the start-up phase (Flash initialization only needs stable V18, but does not need
stable system clock since an internal dedicated oscillator is used).