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| 型號： | SM65MLVD205AD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 中文描述： | 多點LVDS線路驅(qū)動器和接收器 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 517K |
| 代理商： | SM65MLVD205AD |
www.ti.com
A/Y
B/Z
0 V or V
CC
1.62 k
,
±
1%
V
A
, V
B
, V
Y
or V
Z
tc(n)
1/f0
0 V
0 V
Period Jitter
0 V Diff
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
V
A
-V
B
or V
Y
-V
Z
V
A
-V
B
or V
Y
-V
Z
CLOCK
INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
V
CC
V
CC
/2
t
jit(per)
=
t
c(n)
-1/f0
t
jit(pp)
0 V
V
CC
V
CC
/2
0 V
V
A
-V
B
or V
Y
-V
Z
V
A
-V
B
or V
Y
-V
Z
(V
A
+ V
B
)/2
I
O
R
V
CM
V
O
V
ID
V
A
I
A
A
B
I
B
V
B
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573–DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Maximum Steady State Output Voltage
A.
B.
C.
D.
All input pulses are supplied by an Agilent 81250 Stimulus System.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter is measured using a 50 MHz 50
±
1% duty cycle clock input.
Peak-to-peak jitter is measured using a 100Mbps 2
15
–1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
Figure 9. Receiver Voltage and Current Definitions
9
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