參數(shù)資料
型號： SM65MLVD205AD
廠商： Texas Instruments, Inc.
英文描述： MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
中文描述： 多點(diǎn)LVDS線路驅(qū)動器和接收器
文件頁數(shù)： 6/26頁
文件大?。?/td> 517K
代理商： SM65MLVD205AD
www.ti.com
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573–DECEMBER 2003
PARAMETER
TEST CONDITIONS
MIN TYP
(1)
2
2
2
2
MAX
3.5
3.5
3.2
3.2
150
0.9
UNIT
ns
ns
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
t
pLH
t
pHL
t
r
t
f
t
sk(p)
t
sk(pp)
t
jit(per)
t
jit(pp)
t
PHZ
t
PLZ
t
PZH
t
PZL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t
pHL
– t
pLH
|)
Part-to-part skew
Period jitter, rms (1 standard deviation)
(2)
Peak-to-peak jitter
(2)(4)
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
2.5
2.5
2.6
2.6
30
See
Figure 5
50 MHz clock input
(3)
100 Mbps 2
15
-1 PRBS input
(5)
2
3
55
4
4
4
4
150
7
7
7
7
See
Figure 6
(1)
(2)
(3)
(4)
(5)
All typical values are at 25
°
C and with a 3.3-V supply voltage.
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
t
= t
= 0.5 ns (10% to 90%), measured over 30 k samples.
Peak-to-peak jitter includes jitter due to pulse skew (t
).
t
r
= t
f
= 0.5 ns (10% to 90%), measured over 100 k samples.
TYP
(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1)
t
PLH
t
PHL
t
r
t
f
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
Output signal fall time
2
2
1
1
3.6
3.6
6
6
ns
ns
ns
ns
ps
ps
ns
ps
ps
ps
ns
ns
ns
ns
2.3
2.3
300
500
C
L
= 15 pF, See
Figure 10
Type 1
Type 2
100
300
t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|)
t
sk(pp)
t
jit(per)
Part-to-part skew
(2)
Period jitter, rms (1 standard deviation)
(3)
1
7
50 MHz clock input
(4)
4
Type 1
Type 2
200
225
700
800
10
10
15
15
t
jit(pp)
Peak-to-peak jitter
(3)(5)
100 Mbps 2
15
–1 PRBS input
(6)
t
PHZ
t
PLZ
t
PZH
t
PZL
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
6
6
See
Figure 11
10
10
(1)
(2)
(3)
(4)
All typical values are at 25
°
C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
V
= 200 mV
pp
(LVD200A, 202A), V
ID
= 400 mV
pp
(LVD204A, 205A), V
cm
= 1 V, t
r
= t
f
= 0.5 ns (10% to 90%), measured over 30 k
samples.
Peak-to-peak jitter includes jitter due to pulse skew (t
).
V
= 200 mV
pp
(LVD200A, 202A), V
ID
= 400 mV
pp
(LVD204A, 205A), V
cm
= 1 V, t
r
= t
f
= 0.5 ns (10% to 90%), measured over 100 k
samples.
(5)
(6)
6
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