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| 型號： | SM65MLVD205AD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 中文描述： | 多點LVDS線路驅(qū)動器和接收器 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 517K |
| 代理商： | SM65MLVD205AD |
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1.2 V
1.0 V
t
pLH
0.2 V
0 V
-0.2 V
V
A
V
B
V
ID
90%
V
OH
V
CC
/2
V
OL
t
pHL
10%
t
f
t
r
V
O
V
O
V
ID
V
B
V
A
C
L
15 pF
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573–DECEMBER 2003
Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
V
ID
2.400
–2.400
0.050
–0.050
0.050
–0.050
RESULTING COMMON-
MODE INPUT VOLTAGE
V
IC
1.200
1.200
3.4
3.4
–1
–1
APPLIED VOLTAGES
RECEIVER
(1)
OUTPUT
V
IA
2.400
0.000
3.425
3.375
–0.975
–1.025
V
IB
0.000
2.400
3.335
3.425
–1.025
–0.975
H
L
H
L
H
L
(1)
H= high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
V
ID
2.400
–2.400
0.150
0.050
0.150
0.050
RESULTING COMMON-
MODE INPUT VOLTAGE
V
IC
1.200
1.200
3.4
3.4
–1
–1
APPLIED VOLTAGES
RECEIVER
OUTPUT
(1)
V
IA
2.400
0.000
3.475
3.425
–0.925
–0.975
V
IB
0.000
2.400
3.325
3.375
–1.075
–1.025
H
L
H
L
H
L
(1)
H= high level, L = low level, output state assumes receiver is enabled (RE = L)
A.
All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, frequency = 1 MHz,
duty cycle = 50
±
5%. C
L
is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture
capacitance within 2 cm of the D.U.T.
The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
B.
10
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