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| 型號： | SM65MLVD205AD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 中文描述： | 多點LVDS線路驅(qū)動器和接收器 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 517K |
| 代理商： | SM65MLVD205AD |
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
AB
or V
YZ
A/Y
B/Z
I
A
or I
Y
V
B
or V
Z
V
A
or V
Y
V
OS
V
A
+ V
B
2
V
I
D
V
CC
V
Y
+ V
Z
2
or
I
B
or I
Z
I
I
V
AB
or V
YZ
49.9
3.32 k
3.32 k
_
+
-1 V
≤
V
test
≤
3.4 V
A/Y
B/Z
D
V
OS
R1
24.9
A/Y
C3
2.5 pF
V
OS(PP)
V
OS(SS)
V
OS(SS)
≈
1.3 V
B/Z
A/Y
≈
0.7 V
B/Z
D
R2
24.9
C1
1 pF
C2
1 pF
V
Test
+
-
A/Y
B/Z
I
OS
0 V or V
CC
-1 V or 3.4 V
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573–DECEMBER 2003
Figure 1. Driver Voltage and Current Definitions
A.
All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A.
All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, pulse frequency = 1
MHz, duty cycle = 50 ± 5%.
C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
The measurement of V
OS(PP)
is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
B.
C.
D.
Figure 4. Driver Short-Circuit Test Circuit
7
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