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參數(shù)資料
| 型號： | SM65MLVD205AD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 中文描述： | 多點LVDS線路驅(qū)動器和接收器 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 517K |
| 代理商： | SM65MLVD205AD |
www.ti.com
tc(n)
1/f0
Period Jitter
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
CLOCK INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
t
jit(per)
=
t
c(n)
-1/f0
t
jit(pp)
V
A
-V
B
INPUTS
V
A
-V
B
0.2 V - Type 1
0.4 V - Type 2
V
IC
1 V
V
OH
V
CC
/2
V
OL
V
OH
V
OL
V
CC
/2
V
OH
V
OL
V
CC
/2
V
A
V
B
PIN ASSIGNMENTS
SN65MLVD202AD (Marked as MLVD202A)
SN65MLVD205AD (Marked as MLVD205A)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
V
CC
V
CC
A
B
Z
Y
NC
NC - No internal connection
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
SN65MLVD200AD (Marked as MF200A)
SN65MLVD204AD (Marked as MF204A)
(TOP VIEW)
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573–DECEMBER 2003
A.
B.
C.
D.
All input pulses are supplied by an Agilent 8304A Stimulus System.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input.
Peak-to-peak jitter is measured using a 100 Mbps 2
15
-1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
12
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