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| 型號(hào)： | SII1160 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | CASE,HEAVY-DUTY POLY,201407, FOAM FILLED,w/HANDLE,BLACK |
| 中文描述： | PanelLink發(fā)射機(jī) |
| 文件頁(yè)數(shù)： | 9/33頁(yè) |
| 文件大?。?/td> | 494K |
| 代理商： | SII1160 |
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SiI
1160 PanelLink Transmitter
Data Sheet
5
SiI
-DS-0126-B
DC Specifications
Under normal operating conditions, with R
EXT_SWING
= 510
and using source termination, unless otherwise
specified.
Symbol
V
OD
Parameter
Conditions
Min
510
Typ
550
Max
590
Units
Differential Voltage
Single ended peak to peak
amplitude
Differential High-level Output
Voltage
Differential Output Short
Circuit Current
Power-down Current
2
Transmitter Supply Current
R
LOAD
= 50
mV
V
DOH
AVCC
V
I
DOS
V
OUT
= 0 V
5
μ
A
I
PD
I
CCT
IDCK= 165 MHz, two pixel per
clock mode
IVCC = VCC, Worst Case Pattern
3
5
mA
mA
140
200
Notes
1. Guaranteed by design.
2. Assumes all inputs to the transmitter are not toggling.
3. The Worst Case Pattern consists of a black and white checkerboard pattern, each checker one pixel wide.
AC Specifications
Under normal operating conditions with source termination and the recommended R
EXT_SWING
value unless
otherwise specified.
Symbol
T
CIP
F
CIP
T
CIP
F
CIP
T
CIH
T
CIL
T
SIDF
Parameter
Conditions
Min
6
25
12
12
2
2
1.5
Max
40
165
80
81
Units
ns
MHz
ns
MHz
ns
ns
ns
IDCK Period, 1 Pixel/Clock
IDCK Frequency, 1 Pixel/Clock
IDCK Period, 2 Pixels/Clock
IDCK Frequency, 2 Pixels/Clock
IDCK High Time at 165MHz
IDCK Low Time at 165MHz
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Setup Time to IDCK falling edge
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Hold Time from IDCK falling edge
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Setup Time to IDCK rising edge
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Hold Time from IDCK rising edge
VSYNC, HSYNC, and CTL[3:1] Delay from DE falling
edge
VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge
1
DE high time
1
DE low time
1
SDA Data Valid Delay from SCL high to low transition
ISEL/RST Signal High Time required for valid I
2
C reset
EDGE = 0
T
HIDF
EDGE = 0
1.5
ns
T
SIDR
EDGE = 1
1.5
ns
T
HIDR
EDGE = 1
1.5
ns
T
DDF
T
CIP
ns
T
DDR
T
HDE
T
LDE
T
I2CDVD
T
RESET
C
L
= 400pf
T
CIP
ns
ns
ns
ns
μs
8191T
CIP
128T
CIP
50
1000
Notes
1. Guaranteed by design.
2. All TMDS signaling is guaranteed to meet the DVI 1.0 specifications.
3. All Standard mode I
2
C (100kHz and 400kHz) timing requirements are guaranteed by design.
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