參數(shù)資料
型號(hào)： SII1160
廠商： Silicon Image, Inc.
英文描述： CASE,HEAVY-DUTY POLY,201407, FOAM FILLED,w/HANDLE,BLACK
中文描述： PanelLink發(fā)射機(jī)
文件頁(yè)數(shù)： 4/33頁(yè)
文件大?。?/td> 494K
代理商： SII1160
SiI
1160 PanelLink Transmitter
Data Sheet
LIST OF TABLES
Table 1. General I
2
C Register Bits................................................................................................................13
Table 2. Dual Zone PLL I
2
C Control Register Bits........................................................................................14
Table 3. One Pixel/Clock Input/Output TFT Mode........................................................................................15
Table 4. Two Pixels/Clock Input/Output TFT Mode ......................................................................................16
Table 5. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode................................17
Table 6. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode................................18
Table 7. Two Pixels/Clock Input with One Pixel/Clock Output TFT Mode....................................................19
Table 8. New Pin Functions for
SiI
1160 Tx..................................................................................................20
Table 9. Power Consumption Characteristics ..............................................................................................22
Table 10. Recommended Components for Bypass and Decoupling Circuits...............................................23
Table 11. Routing Guidelines for DVI Traces................................................................................................27
LIST OF FIGURES
Figure 1. System Block Diagram – Typical Application.................................................................................. 1
Figure 2. Pin Diagram for
SiI
1160 ................................................................................................................. 2
Figure 3. Functional Block Diagram ............................................................................................................... 3
Figure 4. Clock Cycle High/Low Times........................................................................................................... 6
Figure 5. Input Data Setup/Hold Time to IDCK .............................................................................................. 6
Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE...................................................................... 6
Figure 7. DE High and Low Times.................................................................................................................. 6
Figure 8. Reset Timing at Power-Up or Prior to First I
2
C Access................................................................... 7
Figure 9. I
C Byte Read................................................................................................................................ 11
Figure 10. I
2
C Byte Write.............................................................................................................................. 11
Figure 11. Voltage Regulation using LM317EMP.........................................................................................20
Figure 12. Planned Spread Spectrum Support Circuit .................................................................................21
Figure 13. Typical Reset Circuit....................................................................................................................22
Figure 14. Decoupling and Bypass Capacitor Placement............................................................................23
Figure 15. Decoupling and Bypass Schematic.............................................................................................23
Figure 16. Series Input Damping Resistors for Driving Source ...................................................................24
Figure 17. Differential Output Source Terminations ....................................................................................24
Figure 18. Source Termination Layout Illustration........................................................................................25
Figure 19. Example of Incorrect Differential Signal Routing ........................................................................26
Figure 20. Example of Correct Differential Signal Routing...........................................................................26
Figure 21. Differential Trace Routing to DVI Connector (Top Side View) ....................................................26
Figure 22. 100-pin TQFP Package Dimensions (JEDEC code MS-026-AED)............................................28
SiI
-DS-0126-B
iv
相關(guān)PDF資料
PDF描述
SiI1160CTU PanelLink Transmitter
SII1161 PanelLink Receiver
SiI1161CT100 PanelLink Receiver
SiI1161CTU PanelLink Receiver
SII1162 PanelLink Transmitter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII1160CTU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter
SII1161 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver
SII1161CT100 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver
SII1161CTU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver
SII1162 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*