參數(shù)資料
型號： SII1160
廠商： Silicon Image, Inc.
英文描述： CASE,HEAVY-DUTY POLY,201407, FOAM FILLED,w/HANDLE,BLACK
中文描述： PanelLink發(fā)射機
文件頁數(shù)： 13/33頁
文件大?。?/td> 494K
代理商： SII1160
SiI
1160 PanelLink Transmitter
Data Sheet
9
SiI
-DS-0126-B
Power Management Pins
Pin Name
PD
Pin #
26
Type
In
Description
Power Down (active LOW). A HIGH level indicates normal operation. A LOW level
indicates power down mode. During power down mode, all data (DIE/DIO[23:0]), data
enable (DE), clock (IDCK) and control signals (HSYNC, VSYNC, CTL[3:1]), input buffers
are disabled, all output buffers are tri-stated and all internal circuitry is powered down.
When the I
C interface is enabled (ISEL/RST=LOW), this pin is ignored and the PD
register bit is used instead. Tie this pin low if not used.
Differential Signal Data Pins
Pin Name
TX0+
TX0-
TX1+
TX1-
TX2+
TX2-
TXC+
TXC-
EXT_SWING
Pin #
40
39
43
42
46
45
35
34
32
Type
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor determines
the amplitude of the voltage swing. A smaller resistor value sets a larger voltage swing
and vice versa. For remote display applications with source termination, a 510
resistor
is recommended (see page 24). Without the source termination, use a 560
resistor.
Description
TMDS Low Voltage Differential Signal input data pairs.
These pins are tri-stated when PD is asserted.
TMDS Low Voltage Differential Signal input clock pair.
These pins are tri-stated when PD is asserted.
Local Control (I
2
C) Interface
The transmitter can operate with or without an I
2
C interface connection. Refer to the Feature Information section
for details on using the I
2
C registers.
Pin Name
ISEL/RST
Pin #
87
Type Description
In
I
2
C Interface Select. If LOW, then the I
2
C interface is active. If HIGH, the interface is
inactive and chip configuration is taken from strap and default settings. This pin also acts
as an asynchronous reset to the I
C interface controller. Switching this input from HIGH to
LOW after a minimum T
RESET
high time resets the I
C logic.
Out
Monitor Sense. The behavior of this output depends on whether the I
2
C interface is
enabled or disabled.
No I
2
C (ISEL = HIGH)
MSEN=HIGH: a powered on receiver is detected at the TMDS outputs.
MSEN=LOW: a powered on receiver is not detected.
This Receiver Sense function can only be used in DC-coupled systems.
I
2
C enabled (ISEL = LOW)
The output is programmable through the I
2
C interface and can indicate the Hot
Plug or Receiver Sense signal state, or can instead generate a status change interrupt for
those signals.
This pin is an open collector output. An external pull-up resistor (5K
recommended) is
required on this pin if the MSEN signal will be used. Otherwise the signal should be tied
low.
In
I
2
C Clock. When the I
2
C interface is enabled (ISEL=LOW), this pin acts as the I
2
C clock
input. This pin is an open collector output. It must be pulled high to VCC through a
resistor; a value of 2.2K
is recommended for I
2
C applications, 2-5K
otherwise. This pin
is not 5V-tolerant.
In/Out I
2
C Data. When the I
2
C interface is enabled (ISEL=LOW), this pin acts as the I
2
C data
input and output. This pin is an open collector output. It must be pulled high to VCC
through a resistor; a value of 2.2K
is recommended for I
2
C applications, 2-5K
otherwise. This pin is not 5V-tolerant.
MSEN
21
SCL
20
SDA
23
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