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參數(shù)資料
| 型號： | SiI1151CLU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK |
| 中文描述： | PanelLink接收機(jī) |
| 文件頁數(shù)： | 35/44頁 |
| 文件大?。?/td> | 377K |
| 代理商： | SII1151CLU |
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SiI
1151
PanelLink Receiver
Data Sheet
31
SiI
-DS-0023-C
Design Recommendations
The following sections describe recommendations for robust board design with this PanelLink receiver.
Designers should include provision for these circuits in their design, and adjust the specific passive component
values according to the characterization results.
Differences Between
SiI
151B and
SiI
1151
The RESERVED pin (pin 99) on the
SiI
151B is required to be tied HIGH for normal operation. On the
SiI
1151
part, pin 99 is defined so that tying it HIGH maintains pin compatibility with the
SiI
151B. In this mode, the
SiI
1611 chip meets all operational and timing specifications of the
SiI
151B with these exceptions.
Active mode power consumption is higher on the
SiI
1151 part due to the new equalizer circuitry. Refer to
Table 1 for actual values.
T
FSC
is shorter and more predictable due to improved logic implementation.
Selecting
SiI
1151 (Programmable) Mode
To use the programmable features of the
SiI
1151 part:
Tie pin 99 (the MODE signal) LOW
Tie pin 7 (the I2C_MODE# signal) LOW
The chipset registers are now accessible through standard I
2
C signaling up to 400kHz through pins 3 (SDA) and
100 (SCL). Note that these pins must be connected through pullups (2k
recommended) to 3.3V for correct
operation. In this mode, several pins change their functionality from the
SiI
151B standard as shown in Table 17.
Table 17. New Pin Functions for
SiI
1151 in Programmable Mode
MODE tied HIGH
Chip is in
SiI
151B Compatible Mode
STAG_OUT#
Pin
99
7
MODE tied LOW
Chip is in
SiI
1151 I
2
C Programmable Mode
I2C_MODE#
HIGH: Not Supported
LOW: Chip is in I
C Programmable Mode
SDA
SCL
3
ST
OCK_INV
100
Programmable Mode Reset Recommendations
For programmable mode operation, the
SiI
1151 I
2
C logic
must be reset at least once
, at power-up time, for
reliable operation.
The reset is triggered whenever PD# (pin 2) transitions from LOW to HIGH after VCC has reached its nominal
operating voltage.
If the host controls PD#, this reset occurs automatically whenever the chip is brought from power-down mode to
active mode. However, if the host is not controlling PD# and the pin is simply tied to VCC, there will not be
sufficient time during initial voltage ramp to reset the logic. Figure 21 illustrates the timing requirement.
Figure 21. RESET Generation Delay
Vcc
Internal gate
turn-on voltage
Internal I
2
C RESET
t
RESET
= 10
μ
s min
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