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| 型號(hào)： | SiI1151CLU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK |
| 中文描述： | PanelLink接收機(jī) |
| 文件頁(yè)數(shù)： | 12/44頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | SII1151CLU |
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SiI
1151
PanelLink Receiver
Data Sheet
SiI
-DS-0023-C
8
SiI
151B (Compatible) Mode AC Specifications
AC timings are provided here in setup/hold format at 112MHz for ease of direct comparison to the
SiI
151B part.
Timing specifications in Table 4 apply to worst-case one pixel per clock mode. For other modes and frequencies
use the
SiI
1151 Mode timings and calculation methodology, “Calculating Setup and Hold Times” on Page 12.
Table 4.
SiI
151B Mode AC Specifications
Strap option: ST=0 (Low Drive Strength)
Parameter
Conditions
C
L
=5pF
C
L
=5pF
C
L
=5pF
C
L
=5pF
Limits (ns)
Data, HSYNC, VSYNC
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
ODCK, DE
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
Timing @ 112MHz
Max
2.5
2.0
Max
1.5
1.7
Min
Min
OCK_INV=0
2.1
1.4
4.0
4.8
OCK_INV=1
2.4
1.6
3.6
3.8
T
SETUP
T
HOLD
Data
DE, HSYNC, VSYNC
Data
DE, HSYNC, VSYNC
C
L
=5pF
C
L
=5pF
C
L
=5pF
C
L
=5pF
Strap option: ST=1 (High Drive Strength)
Parameter
Conditions
C
L
=10pF
C
L
=10pF
C
L
=10pF
C
L
=10pF
Limits (ns)
Data, HSYNC, VSYNC
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
ODCK, DE
D
HLT
1-to-0 Transition
D
LHT
0-to-1 Transition
Timing @ 112MHz
Max
2.5
2.0
Max
1.2
1.4
Min
Min
OCK_INV=0
2.1
1.8
4.0
4.3
OCK_INV=1
2.4
2.3
3.4
3.3
T
SETUP
T
HOLD
Data
DE, HSYNC, VSYNC
Data
DE, HSYNC, VSYNC
C
L
=10pF
C
L
=10pF
C
L
=10pF
C
L
=10pF
Notes
1. All transitions are specified at worst case of 70oC with minimum VCC.
2. ODCK and DE output pins should be loaded with 10pF when ST=0 and 20pF when ST=1. If layout requires only a
point-to-point, one load net, a discrete 10pF capacitor should be added to the net to create these loads. See Figure
3.
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