參數(shù)資料
型號： SiI1151CLU
廠商： Silicon Image, Inc.
英文描述： CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK
中文描述： PanelLink接收機
文件頁數(shù)： 17/44頁
文件大?。?/td> 377K
代理商： SII1151CLU
SiI
1151
PanelLink Receiver
Data Sheet
13
SiI
-DS-0023-C
Table 7 shows the calculations required for determining setup and hold timings using the clock period T
ODCK
specific to the clock frequency, also bringing in the clock duty cycle as required when OCK_INV=0. The setup
and hold times apply to DE, VSYNC, HSYNC and Data output pins, as long as the appropriate T
CK2OUT
value is
used for the calculation in each case. The table also shows calculated setup and hold times for commonly used
ODCK frequencies.
Table 7. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=0
Symbol
T
SU
Parameter
Frequency
T
ODCK
40 ns
12 ns
9 ns
40 ns
12 ns
9 ns
T
CK2OUT
(data)
Max
=1.5
Min
=0.4
Result
Data Setup Time
to ODCK
=T
ODCK
*T
DUTY
{min)
-T
CK2OUT
{max}
Data Hold Time
from ODCK
=T
ODCK
* (1 - T
DUTY
{max})
+ T
CK2OUT
{min}
25 MHz
82.5 MHz
112 MHz
25 MHz
82.5 MHz
112 MHz
=40*40% - 1.5 = 14.5ns
=12*40% - 1.5 = 3.3ns
=9*40% - 1.5 = 2.1ns
=40*40% + 0.4 = 16.4ns
=12*40% + 0.4 = 5.2ns
=9*40% + 0.4 = 4.0ns
T
HD
OCK_INV=1 Case
For OCK_INV=1, the timing is similar to that previously discussed. The worst-case setup time occurs when the
clock to output delay is at a maximum (latest data) and the ODCK duty cycle is at a minimum (earliest falling
edge). Conversely, the worst case hold time occurs when the clock to output delay is at a minimum (earliest next
data) and the ODCK duty cycle is at a maximum (latest falling edge). This timing relationship is shown in Figure
6. The rising active ODCK edge is shown with an arrowhead.
Figure 6. Receiver Output Setup and Hold Times – OCK_INV=1
Note:
For Staggered Output timing in 2Pix/clk mode, refer to Figure 15.
T
DUTY
= min
T
= max
External clock
ODCK
with
OCK_INV=1
Q
DE
VSYNC
HSYNC
50%
T
HD
T
SU
T
= min
T
DUTY
= max
50%
Edge used
internally to clock
out Data (Q), DE,
VSYNC, HSYNC
T
DLY
-
inverter delays
External logic uses
this rising clock edge
to sample data
Internal
Clock
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