- 您現在的位置：買賣IC網 > PDF目錄365565 > SiI1151CLU (Silicon Image, Inc.) CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK PDF資料下載
參數資料
| 型號： | SiI1151CLU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK |
| 中文描述： | PanelLink接收機 |
| 文件頁數： | 16/44頁 |
| 文件大小： | 377K |
| 代理商： | SII1151CLU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
SiI
1151
PanelLink Receiver
Data Sheet
SiI
-DS-0023-C
12
Calculating Setup and Hold Times
Output setup and hold times between video output clock (ODCK) and video data (including HSYNC, VSYNC and
DE) are functions of the worst case duty cycle specification for ODCK and the worst case clock to output delay.
For the
SiI
1151 output pins, only the minimum output setup and hold times are critical.
The
SiI
1151 provides the OCK_INV feature, described on page 22, to allow external logic to decode data with
either a rising or falling clock edge.
OCK_INV=0 Case
For OCK_INV=0, the worst-case setup time occurs when the clock to output delay is at a maximum (latest data)
and the ODCK duty cycle is at a minimum (earliest falling edge). Conversely, the worst case hold time occurs
when the clock to output delay is at a minimum (earliest next data) and the ODCK duty cycle is at a maximum
(latest falling edge). This is shown in Figure 5. The falling active ODCK edge is shown with an arrowhead.
Figure 5. Receiver Output Setup and Hold Times – OCK_INV=0
Note:
For Staggered Output timing in 2Pix/clk mode, refer to Figure 15.
Actual setup and hold times can be derived from the clock period at the operating frequency of interest. Clock
duty cycle must also be taken into account when calculating setup and hold times.
Setup Time
to ODCK: T
ODCK
*T
DUTY
{min} - T
CK2OUT
{max}
Hold Time
from ODCK: T
ODCK
* (1 - T
DUTY
{max}) + T
CK2OUT
{min}
T
DUTY
= min
T
= max
External clock
ODCK
with
OCK_INV=0
Q
DE
VSYNC
HSYNC
50%
T
HD
T
SU
T
= min
T
DUTY
= max
50%
Rising edge used
internally to clock
out Data (Q), DE,
VSYNC, HSYNC
T
DLY
-
inverter delays
External logic uses
this falling clock edge
to sample data
Internal
Clock
相關PDF資料 |
PDF描述 |
|---|---|
| SII1160 | CASE,HEAVY-DUTY POLY,201407, FOAM FILLED,w/HANDLE,BLACK |
| SiI1160CTU | PanelLink Transmitter |
| SII1161 | PanelLink Receiver |
| SiI1161CT100 | PanelLink Receiver |
| SiI1161CTU | PanelLink Receiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SII1160 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
| SII1160CTU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
| SII1161 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1161CT100 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1161CTU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。