7. 16-Bit RAM Address Summary1 All" />
參數(shù)資料
型號： SI3232DCX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 119/128頁
文件大?。?/td> 0K
描述： DAUGHTER CARD W/DISCRETE INTRFC
標準包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3232
已供物品： 板，CD
Si3232
90
Preliminary Rev. 0.96
Not
Recommended
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7. 16-Bit RAM Address Summary1
All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a
similar manner as the 8-bit control registers except that the data are twice as long. In addition, one additional
READ cycle is required during READ operations to accommodate the one-deep pipeline architecture. (See "4.16.
SPI Control Interface" on page 50 for more details). All internal RAM addresses are assigned a default value of
zero during initialization and following a system reset. Unless otherwise noted, all RAM addresses use a 2s
complement, MSB first data format (ordered alphabetically by mnemonic).
RAM
Addr
Mnemonic
Description
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Type
Ex.
Hex
Ex.
Dec
Unit
Battery Selection and VOC Tracking
31
BATHTH
High Battery
Switch Threshold
BATHTH[14:7]2
Init
0E54
18
V
34
BATLPF
Battery Tracking
Filter Coeff
BATLPF[15:3]
Init
0A08
10
32
BATLTH
Low Battery Switch
Threshold
BATLTH[14:7]2
Init
0D88
17
V
33
BSWLPF
RING Voltage Filter Coeff
BSWLPF[15:3]
Init
0A08
10
Speedup
36
CMHITH
Speedup Threshold—
High Byte
CMHITH[15:0]
Init
0001
1
V
35
CMLOTH
Speedup Threshold—
Low Byte
CMLOTH[15:0]
Init
07F5
10
V
SLIC Diagnostics Filter
53
DIAGAC
SLIC Diags AC
Detector Threshold
DIAGAC[15:0]
Diag
V
54
DIAGACCO
SLIC Diags AC Filter Coeff
DIAGACCO[15:3]
Diag
7FF8
127.3
Hz
51
DIAGDC
SLIC Diags dc Output
DIAGDC[15:0]
Diag
V
52
DIAGDCCO
SLIC Diags dc Filter Coeff
DIAGDCCO[15:3]
Diag
0A08
10
Hz
55
DIAGPK
SLIC Diags Peak
Detector
DIAGPK[15:0]
Diag
V
Loop Currents
9
ILONG
Longitudinal Current Sense
Value
ILONG[15:0]2
DIag
mA
8
ILOOP
Loop Current Sense Value
ILOOP[15:0]2
Diag
mA
18
IRING
Q5 Current Measurement
IRING[15:0]
Diag
mA
16
IRINGN
Q3 Current Measurement
IRINGN[15:0]
Diag
mA
15
IRINGP
Q2 Current Measurement
IRINGP[15:0]
Diag
mA
19
ITIP
Q6 Current Measurement
ITIP[15:0]
Diag
mA
17
ITIPN
Q4 Current Measurement
ITIPN[15:0]
Diag
mA
14
ITIPP
Q1 Current Measurement
ITIPP[15:0]
Diag
mA
Loop Closure Detection
24
LCRDBI
Loop Closure Detection
Debounce Interval
LCRDBI[15:0]2
Init
000C
15
ms
25
LCRLPF
Loop Closure Filter Coeff
LCRLPF[15:3]
Init
0A10
10
Notes:
1.
RAM values are 2’s complement unless otherwise noted. Any register not listed is reserved and must not be written.
2.
Only positive input values are valid for these RAM addresses.
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