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參數(shù)資料
| 型號： | SI3232DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 82/128頁 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3232 |
| 已供物品： | 板，CD |
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Si3232
Preliminary Rev. 0.96
57
Not
Recommended
fo
r N
ew
D
esi
gn
s
During
RAM
address
accesses,
CONTROL,
ADDRESS, and DATA are captured in the SPI module.
At the completion of the ADDRESS byte of a READ
access, the contents of the channel-based data buffer
are moved into the data register in the SPI for shifting
out during the DATA portion of the SPI transfer. This is
the data loaded into the data buffer in response to the
previous RAM address read request. Therefore, there is
a one-deep pipeline nature to RAM address READ
operations. At the completion of the DATA portion of the
READ cycle, the ADDRESS is transferred to the
channel-based address buffer, and a RAM access
request is logged for that channel. The RAMSTAT bit in
each channel can be polled to monitor the status of
RAM address accesses that are serviced twice per
sample period at dedicated windows in the DSP
algorithm.
There is also a RAM access interrupt in each channel
which, when enabled, indicates that the pending RAM
access request has been serviced. For a RAM WRITE
access, the ADDRESS and DATA is transferred from
the SPI registers to the address and data buffers in the
appropriate channel. The RAM WRITE request is then
logged. As for READ operations, the status of the
pending request can be monitored by either polling the
RAMSTAT bit for the channel or enabling the RAM
access interrupt for the channel. By keeping the
address and data buffers as well as the RAMSTAT
register on a per-channel basis, RAM address accesses
can be scheduled for both channels without interface.
4.18. System Testing
The Si3232 includes a complete suite of test tools that
provide the user with the ability to test the functionality
of the line card as well as detect fault conditions present
on the TIP/RING pair. Using the included loopback test
mode
along
with
the
signal
generation
and
measurement tools, the user can typically eliminate the
need for per-line test relays as well as centralized test
equipment.
4.18.1. Loopback Test Mode
The codec loopback encompasses almost entirely the
electronics of both the transmit and receive paths. The
analog signal at the output of the system receive path
DAC is fed back to the input of the transmit path by way
of a feedback path. (See Figure 37.) The codec
loopback mode is enabled by setting the DLM bit in the
LBCON register. The impedance synthesis is disabled
in this mode.
4.18.2. Line Test and Diagnostics
The Si3232 provides a variety of diagnostics tools that
facilitate
remote
fault
detection
and
parametric
diagnostics on the TIP/RING pair as well as line card
functionality verification. The Si3232 can generate dc
line currents and voltages as well as measure all
resulting line voltage and current levels on TIP, RING, or
across the TIP/RING pair. When used in conjunction
with an external codec that can generate discrete audio
tones and discriminate certain audio frequency bands,
the Si3232 can provide a vehicle to allow remote
diagnostics on the subscriber loop and the line card. All
parameters measured by the Si3232 are stored in
registers for further processing by the codec and DSP,
and all dc generation tools are register-programmable
to allow a software-configurable remote diagnostic
system.
The Si3232’s signal generation and measurement tools
are summarized in Table 32. The accompanying text
describes the methodology that can be used to develop
a fully-programmable test suite to facilitate remote
diagnostics.
Figure 37. Digital Loopback Mode
TIP/
RING
+
ATX
I
BUF
Z
A
Codec
Loopback
To off-chip
ADC
Mute
+
Mute
G
m
ARX
From
off-chip
ADC
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