Idle Channel Noise4
參數(shù)資料
型號: SI3232DC0-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 118/128頁
文件大?。?/td> 0K
描述: DAUGHTER CARD W/SI3200 INTERFACE
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3232
已供物品: 板,CD
Si3232
Preliminary Rev. 0.96
9
Not
Recommended
fo
r N
ew
D
esi
gn
s
Noise Performance
Idle Channel Noise4
C-Message weighted
12
15
dBrnC
Psophometric weighted
–78
–75
dBmP
3 kHz flat
18
dBrn
PSRR from VDD1 – VDD4
RX and TX, dc to 3.4 kHz
40
dB
PSRR from VBAT
RX and TX, dc to 3.4 kHz
60
dB
Longitudinal Performance
Longitudinal to Metallic Bal-
ance (forward or reverse)
200 Hz to 1 kHz
58
63
dB
1 kHz to 3.4 kHz
53
58
dB
Metallic to Longitudinal Bal-
ance
200 Hz to 3.4 kHz
40
dB
Longitudinal Impedance5
200 Hz to 3.4 kHz at TIP or RING
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
50
25
20
Longitudinal Current per Pin5
Active off-hook
200Hz to 3.4kHz
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
4
8
10
mA
Table 4. AC Characteristics (Continued)
(VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value
specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. VDD = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 , ZS = 600 synthesized using RS register coefficients.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz will not exceed –55 dBm.
5. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected such that it can
accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given
application.
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