- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16215 > SI3232DC0-EVB (Silicon Laboratories Inc)DAUGHTER CARD W/SI3200 INTERFACE PDF資料下載
參數(shù)資料
| 型號： | SI3232DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 55/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標準包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3232 |
| 已供物品： | 板，CD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Si3232
32
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.5.1. Loop Closure Detection
Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active or On-
Hook Transmission linefeed states (forward or reverse
polarity). The functional blocks required to implement a
loop closure detector are shown in Figure 14, and the
register set for detecting a loop closure event is
provided in Table 19. The primary input to the system is
the Loop Current Sense value provided by the voltage/
current/power monitoring circuitry and reported in the
ILOOP RAM address. The loop current (ILOOP) is
computed by the ISP using the equations shown below.
Refer to Figure 11 on page 26 for the discrete bipolar
transistor references used in the equation below (Q1,
Q2,
Q5
and
Q6
–
note
that
the
Si3200
has
corresponding MOS transistors). The same ILOOP
equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device. The following equation is
conditioned by the CMH status bit in register LCRRTP
and by the linefeed state as indicated by the LFS field in
the LINEFEED register.
If the CMHITH (RAM 36) threshold is exceeded, the
CMH bit is 1, and IQ1 is forced to zero in the
FORWARD-ACTIVE and TIP-OPEN states, or IQ2 is
forced to zero in the REVERSE-ACTIVE and RING-
OPEN states. The other currents in the equation are
allowed to contribute normally to the ILOOP value.
The conditioning due to the CMH bit (LCRRTP Register)
and LFS field (LINEFEED Register) states can be
summarized as follows:
IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3))
IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7))
The output of the Input Signal Processor is the input to a
programmable digital low-pass filter, which can be used
to remove unwanted ac signal components before
threshold detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LCRLPF RAM
location.
LCRLPF = [(2
f x 4096)/800] x 23
Where f is the desired cutoff frequency of the filter.
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low-pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled
by
programming
a
second
threshold,
LCRONHK, to detect the loop going to an OPEN or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the loop-closure debounce
interval, LCRDBI. There is also a loop-closure mask
interval, LCRMASK, that is used to mask transitions
caused when an internal ringing burst (no dc offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit will be
set to indicate that a valid loop closure has occurred.
Table 18. 3-Battery Switching Components
Component
Value
Comments
D1
200 V, 200 mA
IN4003 or similar
Q1
100 V PNP
CXT5401 or similar
Q2
100 V NPN
CXT5551 or similar
R101
1/10 W, ±5%
2.4 k
for V
DD =3.3 V
3.9 k
for V
DD =5 V
R102
10 k
, 1/10 W, ±5%
R103
402 k
, 1/10 W, ±1%
I
loop
I
Q1
I
Q6
–
I
Q5
I
Q2 in TIP-OPEN or RING-OPEN
I
Q1
I
Q6
–
I
Q5
I
Q2
–
+
2
---------------------------------------------------- in all other states
=
–
+
=
相關PDF資料 |
PDF描述 |
|---|---|
| UPZ2D391MHD | CAP ALUM 390UF 200V 20% RADIAL |
| SI3230PPQX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
| M3UFK-1636R | IDC CABLE - MKS16K/MC16M/MCF16K |
| A3RRB-1018G | IDC CABLE - APR10B/AE10G/APR10B |
| SI3225PPTX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI3232DCX-EVB | 功能描述:子卡和OEM板 Si3232 DAUGHTER CARD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI3232-FQ | 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-FQR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3232-G-FQ | 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-G-FQR | 功能描述:電信線路管理 IC Dual-CH SLIC only Internal 65 Vrms RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。