Table 8. DC Characteristics, VDDA " />
參數(shù)資料
型號(hào): SI3232DC0-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 24/128頁
文件大小: 0K
描述: DAUGHTER CARD W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3232
已供物品: 板,CD
Si3232
12
Preliminary Rev. 0.96
Not
Recommended
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ew
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Table 8. DC Characteristics, VDDA =VDDD =VCC =3.3V
(VDD, VDD1–VDD4 = 3.13 V to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input
Voltage
VIH
0.7 x VDD
—3.47
V
Low Level Input Voltage
VIL
——
0.3 x VDD
V
High Level Output
Voltage
VOH
IO =4mA
VDD – 0.6
V
Low Level Output
Voltage
VOL
SDO, INT, SDITHRU
IO =–4mA
——
0.4
V
BATSELa/b, GPOa/b:
IO = –40 mA
0.72
V
SDITHRU Internal
Pullup Resistance
35
50
k
GPO Relay Driver
Source Impedance
ROUT
VDD1–VDD4 =3.13V,
IO <28mA
—63
GPO Relay Driver Sink
Impedance
RIN
VDD1–VDD4 =3.13V,
IO <85mA
—11
Input Leakage Current
IL
——
±10
A
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Table 9. Switching Characteristics—General Inputs
(VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Rise Time, RESET
tr
——
5
ns
RESET Pulse Width*
trl
500
ns
RESET Pulse Width*, SDI Daisy Chain Mode
trl
6—
s
*Note: The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 k
per device.
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