(VDD
參數(shù)資料
型號: SI3232DC0-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 2/128頁
文件大小: 0K
描述: DAUGHTER CARD W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3232
已供物品: 板,CD
Si3232
10
Preliminary Rev. 0.96
Not
Recommended
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Table 5. Linefeed Characteristics
(VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Loop Current Accuracy
ILIM =18mA
±10
%
DC Open Circuit Voltage
Accuracy
Active Mode; VOC =48V,
VTIP – VRING
——
±4
V
DC Differential Output
Resistance
RDO
ILOOP < ILIM
320
DC On-Hook Voltage
Accuracy—Ground Start
VOHTO
IRING<ILIM; VRING wrt ground
VRING =–51 V
——
±4
V
DC Output Resistance—
Ground Start
RROTO
IRING<ILIM; RING to ground
320
DC Output Resistance—
Ground Start
RTOTO
TIP to ground
300
k
Loop Closure Detect
Threshold Accuracy
ITHR =13mA
±10
±15
%
Ground Key Detect
Threshold Accuracy
ITHR =13mA
±10
±15
%
Ring Trip Threshold
Accuracy
ac Detection, VRING =70VPK,
ITH =80mA
—±4
±5
mA
dc detection,
20 V dc offset, ITH =13mA
—±1.5
±2
mA
Ringing Amplitude*
VRING
Open circuit, VBATH =100 V
93
VPK
5 REN load, RLOOP =0
VBATH =100 V
82
VPK
Sinusoidal Ringing Total
Harmonic Distortion
RTHD
—2—
%
Ringing Frequency Accuracy
f = 16 Hz to 100 Hz
±1
%
Ringing Cadence Accuracy
Accuracy of ON/OFF times
±50
ms
Calibration Time
CAL to CAL bit
600
ms
Loop Voltage Sense
Accuracy
Accuracy of boundaries for each
output Code;
VTIP – VRING =48 V
—±2
±4
%
Loop Current Sense
Accuracy
Accuracy of boundaries for each
output code;
ILOOP =18mA
—±7
±10
%
Power Alarm Threshold
Accuracy
Power Threshold = 300 mW
±25
%
*Note: Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series
protection resistance.
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