參數(shù)資料
型號(hào)： SI3232DC0-EVB
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 48/128頁(yè)
文件大小： 0K
描述： DAUGHTER CARD W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3232
已供物品： 板，CD
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Si3232
26
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.4.2. Loop Voltage and Current Monitoring
The Si3232 continuously monitors the TIP and RING
voltages and currents. These values are available to the
user in registers. An internal 8-bit A/D converter
samples the measured voltages and currents from the
analog sense circuitry and translates them into the
digital domain. The A/D updates the samples at an
800 Hz rate. Two derived values, the loop voltage
(VTIP –VRING) and the loop current are also reported.
For ground start operation, the values reported are
VRING and the current flowing in the RING lead.
Table 14 lists the register set associated with the loop
monitoring functions.
The Si3232 also includes the ability to perform loop
diagnostics functions as outlined in "4.18.2. Line Test
4.4.3. Power Monitoring and Power Fault Detection
The Si3232 line monitoring functions can be used to
protect the high-voltage circuitry against excessive
power dissipation and thermal-overload conditions. The
Si3232 also has the ability to prevent thermal overloads
by regulating the total power inside the Si3200 or in
each of the external bipolar transistors (if using a
discrete linefeed circuit). The DSP engine performs all
power
calculations
and
provides
the
ability
to
automatically transition the device into the OPEN state
and generate a power alarm interrupt when excessive
power is detected. Table 16 describes the register and
RAM locations used for power monitoring.
4.4.4. Transistor Power Equations
(Using Discrete Transistors)
When using the Si3232 along with discrete bipolar
transistors, it is possible to control the total power of the
solution by regulating the power in each discrete
transistor individually. Figure 11 illustrates the basic
transistor-based linefeed circuit for one channel. The
power
dissipation
of
each
external
transistor
is
estimated based on the A/D sample values. The
approximate power equations for each external BJT are
as follows:
PQ1 VCE1 x IQ1 (|VTIP| + 0.75 V) x (IQ1)
PQ2 VCE2 x IQ2 (|VRING| + 0.75 V) x (IQ2)
PQ3 VCE3 x IQ3 (|VBAT| – R7 x IQ5) x (IQ3)
PQ4 VCE4 x IQ4 (|VBAT| – R6 x IQ6) x (IQ4)
PQ5 VCE5 x IQ5 (|VBAT| – |VRING| – R7 x IQ5) x (IQ5)
PQ6 VCE6 x IQ6 (|VBAT| – |VTIP| – R6 x IQ6) x (IQ6)
Figure 11. Discrete Linefeed Circuit for Power Monitoring
Table 15. Register Values for CM Calibration
(600
Impedance Synthesis)
Register
Name
Register
Location
(decimal)
Register
Value
(hexadecimal)
ZRS
33
0x5
ZZ
34
0x1
Q2
Q5
R7
IRINGP
Q9
R7*gain
IRINGN
Q3
RING
Q1
Q6
R6
ITIPP
Q10
R6*gain
ITIPN
Q4
TIP
VBAT
RBQ6
RBQ5
Q8
Q7
82.5
1.74k
82.5
1.74k
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