參數(shù)資料
型號： SI3216MDC1-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 10/122頁
文件大小： 0K
描述： DAUGHTER CARD W/SI3201 INTERFACE
標準包裝： 1
Si3216
Rev. 1.0
107
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.3. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but should be written to zeroes.
Table 40. SLIC Control Indirect Registers Summary
Addr. D15
D14
D13
D12
D11
D10
D9
D8D7D6D5D4D3D2D1
D0
15
LCRT[5:0]
16
RPTP[5:0]
17
CML[5:0]
18
CMH[5:0]
19
PPT12[7:0]
20
PPT34[7:0]
21
PPT56[7:0]
22
NCLR[12:0]
23
NRTP[12:0]
24
NQ12[12:0]
25
NQ34[12:0]
26
NQ56[12:0]
27
VCMR[3:0]
64
VMIND[3:0]
66
LCRTL[5:0]
Table 41. SLIC Control Indirect Registers Description
Addr.
Description
Reference Page
15
Loop Closure Threshold.
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
16
Ring Trip Threshold.
Ring trip detection threshold during ringing.
17
Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
18
Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
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