參數(shù)資料
型號： SI3210PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 81/148頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR SI3210
標準包裝： 1
Si3210/Si3211
38
Rev. 1.61
Not
Recommended
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2.2.3. MOSFET/Transformer Circuit Option Using
the Si3210M
The MOSFET/transformer circuit option (shown in
Figure 11 on page 20) offers higher power efficiencies
across a larger input voltage range. Depending on the
transformer’s primary inductor value and the switching
frequency, the input voltage (VDC) can range from 3.3 V
to 35 V. Therefore, it is possible to power the entire
ProSLIC solution from a single 3.3 V or 5 V power
supply. By nature of a dc-dc converter’s operation, peak
and average input currents can become large with small
input voltages. Consider this when selecting the
appropriate input voltage and power rating for the VDC
power supply (number of REN supported).
For this solution, an N-channel power MOSFET (M1)
switches the current flow through a power transformer,
T1. T1 is specified in “AN45: Design Guide for the
Si3210 DC-DC Converter” and includes several taps on
the primary side to facilitate a wide range of input
voltages. The Si3210M version of the Si3210 must be
used for the application circuit depicted in Figure 11
because the DCFF pin is used to drive M1 directly and,
therefore, must be the same polarity as DCDRV.
DCDRV is not used in this circuit option; connecting
DCFF and DCDRV together is not recommended.
2.2.4. DC-DC Converter Architecture
(Si3210/Si3210M Only)
The control logic for a pulse-width-modulated (PWM)
dc-dc converter is incorporated in the Si3210. Output
pins DCDRV and DCFF are used to switch a bipolar
transistor or MOSFET. The polarity of DCFF is opposite
that of DCDRV.
The dc-dc converter circuit is powered on when the
DCOF
bit
in
the
Powerdown
Register
(direct
Register 14, bit 4) is cleared to 0. The switching
regulator
circuit
within
the
Si3210
is
a
high-
performance, pulse-width modulation controller. The
control pins are driven by the PWM controller logic in
the Si3210. The regulated output voltage (VBAT) is
sensed by the SVBAT pin and is used to detect whether
the output voltage is above or below an internal
reference for the desired battery voltage. The dc
monitor pins, SDCH and SDCL, monitor input current
and voltage to the dc-dc converter external circuitry. If
an overload condition is detected, the PWM controller
will turn off the switching transistor for the remainder of
a
PWM
period
to
prevent
damage
to
external
components. It is important that the proper value of R18
be selected to ensure safe operation. Guidance is given
in AN45.
The PWM controller operates at a frequency set by the
dc-dc Converter PWM register (direct Register 92).
During a PWM period, the outputs of the control pins,
DCDRV and DCFF, are asserted for a time given by the
read-only
PWM
Pulse
Width
register
(direct
Register 94).
The dc-dc converter must be off for some time in each
cycle to allow the inductor or transformer to transfer its
stored energy to the output capacitor, C9. This minimum
off time can be set through the dc-dc Converter
Switching Delay register, (direct Register 93). The
number of 16.384 MHz clock cycles that the controller is
off is equal to DCTOF (bits 0 through 4) plus 4. If the dc
Monitor pins detect an overload condition, the dc-dc
converter interrupts its conversion cycles regardless of
the register settings to prevent component damage.
These inputs should be calibrated by writing the DCCAL
bit (bit 7) of the dc-dc Converter Switching Delay
register, direct Register 93, after the dc-dc converter
has been turned on.
Because the Si3210 dynamically regulates its own
battery supply voltage using the dc-dc converter
controller, the battery voltage, VBAT, is offset from the
negative-most terminal by a programmable voltage,
VOV, to allow voltage headroom for carrying audio
signals.
As mentioned previously, the Si3210 dynamically
adjusts VBAT to suit the particular circuit requirement. To
illustrate this, the behavior of VBAT in the active state is
shown in Figure 19. In the active state, the TIP-to-RING
open circuit voltage is kept at VOC in the constant
voltage region while the regulator output voltage
VBAT =VCM + VOC + VOV.
When the loop current attempts to exceed ILIM, the dc
line driver circuit enters constant current mode allowing
the TIP to RING voltage to track RLOOP. As the TIP
terminal is kept at a constant voltage, it is the RING
terminal voltage that tracks RLOOP and, as a result, the
|VBAT| voltage will also track RLOOP. In this state,
|VBAT|= ILIM x RLOOP + VCM +VOV. As RLOOP decreases
below the VOC/ILIM mark, the regulator output voltage
can continue to track RLOOP (TRACK = 1), or the RLOOP
tracking mechanism is stopped when |VBAT|= |VBATL|
(TRACK = 0). The former case is the more common
application
and
provides
the
maximum
power
dissipation savings. In principle, the regulator output
voltage can go as low as |VBAT|=VCM+ VOV, offering
significant power savings.
When TRACK = 0, |VBAT| will not decrease below
VBATL. The RING terminal voltage, however, continues
to decrease with decreasing RLOOP.
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