參數(shù)資料
型號: SI3210PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 100/148頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI3210
標(biāo)準(zhǔn)包裝: 1
Si3210/Si3211
Rev. 1.61
55
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 28. SPI Daisy Chain Mode
CPU
SDO
CS
SDI
CS
SDI
SDITHRU
SDO
CS
SDI
SDITHRU
SDO
C7 C6 C5 C4 C3 C2 C1 C0
R/W
A6 A5 A4 A3 A2 A1 A0
– C7 C6 C5 C4 C3 C2 C1
– – C7 C6 C5 C4 C3 C2
Chip Select Byte
Address Byte
Data Byte
SCLK
SDI0
SDI1
SDI2
SDI3
R/W
A6 A5 A4 A3 A2 A1 A0
R/W
A6 A5 A4 A3 A2 A1 A0
R/W
A6 A5 A4 A3 A2 A1 A0
– – – C7 C6 C5 C4 C3
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the
LSB of the chip select byte for its chip select.
CS
SDI
SDITHRU
SDO
CS
SDI
SDITHRU
SDO
SDI0
SDI3
SDI2
SDI1
D7 D6 D5 D4 D3 D2 D1 D0
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