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| 型號(hào)： | SI3210PPTX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 78/148頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR SI3210 |
| 標(biāo)準(zhǔn)包裝： | 1 |
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Si3210/Si3211
Rev. 1.61
35
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 18. Loop Closure Detection
2.1.6. Loop Closure Transition Detection
A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off-
hook to on-hook; detection occurs while the ProSLIC linefeed is in its on-hook transmission or active states. The
ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks
required to implement loop closure detection are shown in Figure 18. The primary input to the system is the Loop
Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input
Signal Processor when the ProSLIC is in the on-hook transmission or active linefeed state, as indicated by the
Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass
filter, which removes unwanted ac signal components before threshold detection.
The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect Register 28). The
threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains
in its present state unless the input remains in the opposite state for the entire period of time programmed by the
loop closure debounce interval, LCDI (direct Register 69). If the debounce interval has been satisfied, the LCR bit
will change state to indicate that a valid loop closure transition has occurred. A loop closure transition interrupt is
generated if enabled by the LCIE bit (direct Register 22). Table 26 lists the registers that must be written or
monitored to correctly detect a loop closure condition.
2.1.7. Loop Closure Threshold Hysteresis
Silicon revisions C and higher support the addition of programmable hysteresis to the loop closure threshold, which
can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect
Register 28) and LCRTL (indirect Register 43), which set the upper and lower bounds, respectively.
2.1.8. Voltage-Based Loop Closure Detection
Silicon revisions C and higher also support an optional voltage-based loop closure detection mode, which is
enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop
closure threshold register (LCRT), which represents a minimum voltage threshold instead of a maximum current
threshold. If hysteresis is also enabled, LCRT represents the upper voltage boundary, and LCRTL represents the
lower voltage boundary for hysteresis. Although voltage-based loop closure detection is an option, the default
current-based loop closure detection is recommended.
ISP_OUT
NCLR
LCDI
Input
Signal
Processor
Digital
LPF
Loop Closure
Threshold
D ebounce
Filter
+
–
LCR
LCIP
LCIE
Interrupt
Logic
LCS
LVS
LCVE
LFS
LCRTL
LCRT
HYSTEN
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