參數(shù)資料
型號(hào)： sda 9362
廠商： SIEMENS AG
英文描述： DDC-PLUS-Deflection Controller(DDC 過(guò)偏轉(zhuǎn)控制器)
中文描述： DDC的加偏轉(zhuǎn)控制器（DDC的過(guò)偏轉(zhuǎn)控制器）
文件頁(yè)數(shù)： 22/39頁(yè)
文件大?。?/td> 199K
代理商： SDA 9362
SDA 9362
Semiconductor Group
22
1998-02-01
Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this
product influences the horizontal phase at the output HD according to the following
equation:
φ:
variation of horizontal phase at the output HD
(positive values: shift left, negatives values: shift right)
variation of IBEAM input voltage (units: Volt)
864
*
f
H
V
IBEAM
:
CLL:
1)
the factor 52 depends on
V
REFP
Vertical Blanking Time (VBT)
VBT defines the vertical blanking pulse VBL which is part of the output signal SCP. VBL
is synchronized with the leading edge of HSYNC. It always starts and stops at the
beginning of line and never in the center.
a) Case of STE = 0
In this case the control item Vertical blanking time defines the duration of the
V-blanking pulse (VBL) exactly in number of lines. Because of IC internal limitations
16 through 127 lines can be blanked. If BSE = 0 the control item Vertical blanking
time is disabled and always 21 lines (default value if disabled) are blank.
After power on the control bit BSE is 0. Therefore 21 lines will be blanked before any
programming of the IC. If
Vertical Blanking Time
is less or equals 21 lines, VBL
starts (point A in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new
even field) prior to the vertical flyback. Otherwise VBL is concentric to a fictitious
vertical flyback period of 21 lines, that means VBL starts (VBT - 21) / 2 lines at the
end of an odd field or (VBT - 20) / 2 at the end of an even field prior to point A.
Possible start points are only the beginning of line.
φ
V
IBEAM
*
AFC EHT compensation
64
---------------------------------------------------------------- *
52
1
)
CLL
-----------
=
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