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參數(shù)資料
| 型號： | sda 9362 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller(DDC 過偏轉(zhuǎn)控制器) |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器（DDC的過偏轉(zhuǎn)控制器） |
| 文件頁數(shù)： | 13/39頁 |
| 文件大?。?/td> | 199K |
| 代理商： | SDA 9362 |
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SDA 9362
Semiconductor Group
13
1998-02-01
2.3
The circuit is only completely reset at power-on/off (
timing diagram refer 5.3
). If the pin
RESN has L-level or during standby operation some parts of the circuit are not affected
(
timing diagram refer 5.4
):
Reset Modes
Note:
Power-On-Reset state is deactivated after ca. 32 cycles of the X1/X2 oscillator
clock. RESN = Low and standby state are deactivated after ca. 42 cycles of the
CLL clock.
2.4
Frequency Ranges
The allowed deviation of all input line frequencies is max. ±4.5 %.
n
L
:
Number of lines per frame
I:
Interlaced
NI:
Non interlaced
1)
Inactive if HPROT < V2 (typ. 2.4 V)
2)
Can only be read after Power-On-Reset is finished
Power-On-Reset
External Reset
(pin RESN=0)
Active
Active
Active
1)
Ready
Standby Mode
(
I
2
C-Bit STDBY=1)
Active
Active
Active
1)
Ready
HD output
H-protection
V-protection
Ι
2
C Interface (SDA,
SCL)
Ι
2
C Register
01
H
..1B
H
Ι
2
C Register
00
H
, 48
H
Status bit PONRES
V
REFP
V
REFH
,
V
REFL
CPU
High
Inactive
Inactive
Tristate
Set to default values Set to default values Set to default values
Set to default values Not affected
Not affected
Set to 1
2)
Not affected
Not affected
Inactive
Set to 1
Not affected
Not affected
Inactive
Not affected
Not affected
Inactive
Inactive
H
31.25 kHz
V
50 Hz
100 Hz
60 Hz
120 Hz
n
L
625 NI / 1250I
625 I
525 NI / 1050 I
525 I
31.5 kHz
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