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m
formats (readable by I
2
C Bus)
of the input signals
I
Horizontal and vertical compression
Product Brief
DAEDALUS
SDA 9410
D
isplay Processor
a
nd Scan Rate
Conv
e
rter Using Embedded
D
R
A
M Techno
l
ogy
U
nit
s
New Application Modes
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High performance scan rate
converter
supporting true motion
I
Double source input supporting high
resolution frame based PIP and
double window.
Two Input Channels with
Two Data Formats
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Two input channels
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ITU-R 656 data format, 8 wires data
only
or 8 wires including sync
information
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ITU-R 601 4:2:2 data format, lumi-
nance and chrominance parallel
(2x8 wires)
Vertical peaking of the input signal
Noise Reduction
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Motion adaptive spatial and temporal
noise reduction (3D-NR)
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Temporal noise reduction for lumi-
nance and chrominance, frame based
or field based
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Flexible programming of the temporal
noise reduction characteristics
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Automatic measurement of the noise
level
3D Predictive Motion Estimation
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High performance motion estimation
based on block matching algorithm
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Film mode and phase detector 25 Hz
PAL and 30 Hz NTSC - 2-3 pull down
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Global motion flag; readable by I
2
C Bus
Automatic detection of letter box
Embedded DRAM Core
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6 MBit embedded DRAM core for field
memories
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1.1 MBit embedded DRAM core for
line memories, vector memory,
block-to-line converter, line-to-block
converter
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36 kBit SRAM for block matching
Flexible Clock and Synchronization
Concept
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Decoupling of the input and output
clock system possible (free run and
locked modes)
Scan Rate Conversion
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Motion compensated 100/120 Hz
interlaced scan conversion
(Infineon VDU)
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Motion compensated 50/60 Hz pro-
gressive scan conversion (Infineon
VDU) (Vector Driven Upconversion)
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Simple interlaced modes:
ABAB,
AABB, AAAA, BBBB
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True Motion: 50 (60) Hz motion reso-
lution even for 25 (30) Hz film sources
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Large area and line flicker
reduction
Flexible compression and expansion
and expansion of both input channels
individually
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Panorama mode
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Support of split-screen applications
e.g. Text
High Performance Display Processing
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Digital colour transition improvement
(DCTI)
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Digital luminance transition improve-
ment (DLTI)
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Peaking (luminance only)
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Three 9-Bit D/A converters
(two fold oversampling)
Flexible Output Sync Controller
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Flexible positioning of the two output
channels in all application modes
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Flexible height and width of the two
output pictures
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Flexible programming of the output
sync raster
Signal Manipulations
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Still frame or field
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Insertion of coloured background
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Insertion of a selection border
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Adjustable delay between Y and UV
signal at the in- and output
Potential Application
The SDA 9410 is a new component of the
Infineon MEGAVISION IC set for building
high end TV sets
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100/120 Hz interlaced TV sets
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50/60 Hz progressive scan TV sets
Features