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參數(shù)資料
| 型號： | SCM20014 |
| 廠商： | Motorola, Inc. |
| 英文描述： | VGA Digital Image Sensor(VGA數(shù)字圖像傳感器) |
| 中文描述： | VGA數(shù)碼圖像傳感器（顯卡數(shù)字圖像傳感器） |
| 文件頁數(shù)： | 9/54頁 |
| 文件大小： | 911K |
| 代理商： | SCM20014 |
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SCM20014
MOTOROLA
9
Preliminary!! Last Update: 12/14/99
The user can disable this function via the
Capture Mode
Control Register, (Table 24), on page 32
which will al-
low the ASP chain to drift in offset.
Figure 10. FRC Conceptual Block Diagram
2.2.3 Per-Column Digital Offset Voltage Adjust
(DOVA)
A programmable per-column offset adjustment is avail-
able on the SCM20014. A user defined offset value can
be loaded via a 4-bit signed magnitude programming
code. This programmable DOVA allows the user to se-
lect offset coefficients for FPN & PRNU corrections and
channel offset normalization, and is used to correct for
column induced errors. In the default mode, data is au-
tomatically loaded into an onchip RAM that stores 704,
4 bit words representing offset coefficients for each in-
dividual column in the imaging array.
Figure 11
depicts
a conceptual view of how the automatic generation of
the per-column offsets is accomplished.
Figure 11. Conceptual illustration of the auto calib-
eration scheme for offset adjustment
The user can generate and load data for this function as
well. A dark frame can be analyzed to determine the ap-
propriate values to be loaded into the Per-Column
DOVA RAM (
Column DOVA RAM, (Table 19), on page
28
).
When the per-column feature is not used or necessary,
the user loads a 5-bit value into the
Column DOVA DC
Register, (Table 17), on page 27
to perform a global off-
set adjust prior to the gain stages of the ASP.
2.2.4 Digitally Programmable Gain Amplifiers
(DPGA)
Two DPGAs are available in the analog signal process-
ing chain. These are used to perform white balance and
exposure gain functions. Both are linearly programma-
ble via 6-bit registers.
2.2.4.1 White Balance Control PGA
The sensor produces three primary color outputs, Red,
Green and Blue. These are monochrome signals that
represent luminance values in each of the primary col-
ors. When added in equal amounts they mix to make
neutral color. White balancing is a technique where the
gain coefficients of the green(0), red, blue, and green(3)
pixels comprising the Bayer pattern (see
Figure 12
.) are
set so as to equalize their outputs for neutral color
scenes. Since the sensitivity of the two green pixels in
the Bayer pattern may not be equal, an individual color
gain register is provided for each component of the Bay-
er pattern.
Once all color gain registers are loaded with the desired
gain coefficients, white balance is achieved in real time
and in analog space. The appropriate values are select-
ed and applied to the pixel output via a high speed path,
the delay of which is much shorter than the pixel clock
rate. Real time updates can be performed to any of the
gain registers. However, latency associated with the I
2
C
interface should be taken into consideration before
changes occur. In most applications, users will be able
to assign predefined settings such as daylight, fluores-
cent, tungsten, and halogen to cover a wide gamut of il-
lumination conditions.
Both DPGA designs use switched capacitors to mini-
mize accumulated offset and improve measurement ac-
curacy and dynamic range. The white balance gain
registers are 6-bits and can be programmed to allow
gain of 0.9x to 4.6x in steps of 0.06x.
The user programs the individual gain coefficients into
the SCM20014 via the Color Gain Registers (
Table 3
through
Table 6
). For the default Bayer configuration of
the color filter array;
Figure 4
, the Color Gain Register
addresses are as follows: Reg (00h): green pixel of a
+
-
V+
V-
BUF
1X
FRC
V
cm
CLRCA
V
cm
Cap
LRCA
0.1
μ
LRCLMP
LRCLMP
+
BUF
-
1X
CLRCB
Cap
LRCB
0.1
μ
LRCLMP
LRCLMP
Previous
+
-
LRCLMP
V
cm
LRCLMP
Stage
4
Column Offset
Caliberation RAM (704 x 4)
Reference
AutoCal Math
DOVA
ADC
2.0x
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