參數(shù)資料
型號(hào)： SCM20014
廠商： Motorola, Inc.
英文描述： VGA Digital Image Sensor(VGA數(shù)字圖像傳感器)
中文描述： VGA數(shù)碼圖像傳感器（顯卡數(shù)字圖像傳感器）
文件頁(yè)數(shù)： 42/54頁(yè)
文件大小： 911K
代理商： SCM20014
MOTOROLA
SCM20014
42
Preliminary!! Last Update: 12/14/99
6.0 I
2
C Serial Interface
The I
2
C is an industry standard which is also compatible
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I
2
C contains a se-
rial two-wire half-duplex interface that features bidirec-
tional operation, master or slave modes, and multi-
master environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 K
to 10
K
(see
page 49
).
The I
2
C is used to write the required user system data
into the Program Control Registers in the SCM20014.
The I
2
C bus can also read the data in the Program Con-
trol Register for verification or test considerations. The
SCM20014 is a slave only device that supports a maxi-
mum clock rate (SCLK) of 100 kHz while reading or writ-
ing only one register address per I2C start/stop cycle.
The following sections will be limited to the methods for
writing and reading data into the SCM20014 register.
For a complete reference to I
2
C, see “The I
2
C Bus from
Theory to Practice” by Dominique Paret and Carll-
Fenger, published by John Wiley & Sons, ISBN
0471962686.
6.1 SCM20014 I2C Bus Protocol
The SCM20014 uses the I2C bus to write or read one
register byte per start/stop I2C cycle as shown in
Figure
25
and
Figure 26
. These figures will be used to describe
the various parts of the I2C protocol communications as
it applies to the SCM20014.
SCM20014 I2C bus communication is basically com-
posed of following parts: START signal, SCM20014
slave address (0110011
b
) transmission followed by a R/
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment sig-
nal, STOP signal, Repeated START signal, and clock
synchronization.
6.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical “1”),
a master may initiate communication by sending a
START signal. As shown in
Figure 25
, a START signal
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
6.3 Slave Address Transmission
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the SCM20014, start-
ing with the MSB (AD7) is 0110011
b
. The transmitted
calling address on the SDATA line may only be
changed while SCLK is low as shown in
Figure 25
. The
data on the SDATA line is valid on the High to Low sig-
nal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
1 = Read transfer, the slave transitions to a slave
transmitter and sends the data to the master
0 = Write transfer, the master transmits data to the
slave
6.4 Acknowledgment
Only the slave with a calling address that matches the
one transmitted by the master will respond by sending
back an acknowledge bit. This is done by pulling the
SDATA line low at the 9th clock (see
Figure 25
). If a
transmitted slave address is acknowledged, successful
slave addressing is said to have been achieved. No two
7 - 0
Virtual Col-
umn Width
In conjunction with the CFCM Virtual Frame Column Width MSB
(
Table 42
) Register, forms the 14-bit Virtual Frame Column Width
vcw[13:0]. WOI is always top-left justified in Virtual Frame.
vcw
d
minimum = wcw
d
+ 6
11101101
b
(780 col.)
Address
53
h
CFCM Virtual Frame Column Width LSB
Default
ED
h
msb (7)
6
5
4
3
2
1
lsb (0)
vcw[7]
vcw[6]
vcw[5]
vcw[4]
vcw[3]
vcw[2]
vcw[1]
vcw[0]
Table 43. CFCM Virtual Frame Column Width LSB Register
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