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參數(shù)資料
| 型號： | SCM20014 |
| 廠商： | Motorola, Inc. |
| 英文描述： | VGA Digital Image Sensor(VGA數(shù)字圖像傳感器) |
| 中文描述： | VGA數(shù)碼圖像傳感器（顯卡數(shù)字圖像傳感器） |
| 文件頁數(shù)： | 4/54頁 |
| 文件大?。?/td> | 911K |
| 代理商： | SCM20014 |
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MOTOROLA
SCM20014
4
Preliminary!! Last Update: 12/14/99
1.0 SCM20014 Overview
The SCM20014 is a solid state CMOS Active CMOS Im-
ager (ACI
TM
) that integrates the functionality of a com-
plete analog image acquistion, digitizer, and digital
signal processing system on a single chip. The image
sensor comprises a 1/3” format pixel array with 640x480
(VGA) active elements. The image size is fully program-
mable to user defined windows of interest. The pixels
are on a 7.8
μ
m pitch. High sensitivity and low noise are
a characteristic of the pinned photodiode architecture
utilized in the pixels. Optional microlenses are available
to further enhance the sensitivity. The sensor is avail-
able with Bayer patterned Color Filter Arrays (CFAs) for
color output or as a monochrome imager.
Integrated timing and programming controls allow video
(CFCM) or still (SFCM) image capture mode supporting
progressive or interlace scan modes. Frame rates are
programmable while keeping Master Clock frequency
constant. User programmable row and column start/
stop allow windowing to a minimum 1x1 pixel window.
Windowing can also be performed by subsampling in
multiple pixel increments to allow digital zoom.
A high performance analog signal processing chain
helps establish a new benchmark for digital image cap-
ture. The sensor has an unprecedented level of integra-
tion. The analog video output of the pixel array is
processed by an on chip processing pipeline. Correlat-
ed Double Sampling (CDS) eliminates low frequency
correlated noise. The Frame Rate Clamp (FRC) en-
ables real time optical black level calibration and offset
correction. Digitally Programmable Amplifiers (DPGAs)
allow real time color gain correction for Auto White Bal-
ance (AWB) as well as global gain adjustment; offset
calibration can be done on a per column basis or global-
ly. This per-column offset correction can be applied au-
tomatically or by using stored values in the on chip
SRAM. A 10-bit Redundant Signed Digit (RSD) ADC
converts the analog data to a 10-bit digital word stream.
The fully differential analog signal processing pipeline
serves to improve noise immunity, signal to noise ratio,
and system dynamic range.
A digital signal post processing block includes program-
mable features for output data companding and pixel
correction. User programmable thresholding allows re-
placement of pixels beyond preset maximum and mini-
mum levels by average, trailing, or leading pixels. A
noise core allows companding of data that allows users
to accentuate dark pixels. Data companding can be
done by loading any one of eight hard coded compres-
sion curves which performs a 10 to 8 bit transformation
on the data.
The sensor uses an industry standard two line I
2
C serial
interface. It operates with a single 3.3V power supply
with no additional biases and requires only a single
Master Clock for operation upto 13.5MHz. It is housed
in a 48 pin ceramic LCC package.
The SCM20014 is designed taking into consideration in-
terfacing requirements to standard video encoders. In
addition to the 10 bit bayer encoded data stream, the
sensor outputs the valid frame, line and pixel sync sig-
nals needed for encoding. The sensor interfaces with a
variety of commercially available video image proces-
sors to allow encoding into various standard video for-
mats .
The SCM20014 is an elegant and extremely flexible sin-
gle chip solution that simplifies a system designer’s
tasks of image sensing, processing, digital conversion,
and digital signal processing to a high performance, low
cost, low power IC. One that supports among others a
wide range of low power, portable consumer digital im-
aging applications.
2.0 SCM20014 Theory of Operation
This section reviews the concepts behind the operation
of the image sensing and capture mechanisms em-
ployed in the SCM20014.
2.1 Sensor Interface
2.1.1 Pixel Architecture
The SCM20014 ImageMOS
TM
(1) sensor comprises a
640x480 active pixel array and supports both progres-
sive and interlaced scan readout modes. The basic op-
eration of the pixel relies on the photoelectric effect
where due to its physical properties silicon is able to de-
tect photons of light. The photons generate electron-
hole pairs in direct proportion to the intensity and wave-
length of the incident illumination. The application of an
appropriate bias allows the user to collect the electrons
and meter the charge in the form of a useful parameter
such as voltage.
The pixel architecture is based on a four transistor (4T)
Advanced CMOS Imager
TM
(2) pixel which requires all
pixels in a row to have common Reset, Transfer, and
Row Select controls. In addition all pixels have common
supply (V
DD
) and ground (V
SS
) connections. An opti-
mized cell architecture provides enhancements such as
noise reduction, fill factor maximizations, and anti-
blooming. The use of pinned photodiodes (3) and pro-
prietary transfer gate devices in the photoelements
1. ImageMOS is a Motorola trademark
2. Advanced CMOS Imager is a Kodak trademark
3. Patents held jointly by Motorola and Kodak
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