參數(shù)資料
型號(hào)： SCM20014
廠商： Motorola, Inc.
英文描述： VGA Digital Image Sensor(VGA數(shù)字圖像傳感器)
中文描述： VGA數(shù)碼圖像傳感器（顯卡數(shù)字圖像傳感器）
文件頁(yè)數(shù)： 8/54頁(yè)
文件大?。?/td> 911K
代理商： SCM20014
MOTOROLA
SCM20014
8
Preliminary!! Last Update: 12/14/99
T
lim
= 719 * MCLK
period
T
fc
is the minimum amount of time required to perform
a frame clamp with timing overhead and is defined as:
T
fc
= (719 + shs
d
+ shr
d
+ 19) * MCLK
period
The Integration Time for CFCM is defined by a combi-
nation of the width of the WOI and the integration time
register, (
Table 38 on page 39
and
Table 39 on page
40
); and can be expressed as:
Integration Time = (cint
d
+ 1) * T
row
where cint
d
is the number of virtual frame row times de-
sired for integration time. Therefore, the integration time
in CFCM mode can be adjusted in steps of virtual frame
row times. This equation for Integration Time is valid
only for T
row
> (T
lim
* MCLK
period
). For virtual frames
where T
row
< (T
lim
* MCLK
period
), the integration time is
different for the first cint
d
rows and is defined as:
Integration Time
cintdrows
= T
fc
+ (cint
d
* T
row
)
By using the default values in the Virtual Frame defini-
tion and Integration Time registers, an FF
h
loaded into
the Internal Timing Control Register, and assuming a
standard video square pixel clock rate of 12.27Mhz, we
can calculate the frame rate and integration time as:
Row Time = (749 + 16 + 16 + 19) / 12.27e6 = 65.20
μ
s
Frame Time = (524 + 1) * 65.20
μ
s = 34.23ms which re-
sults in a Frame Rate of 29.21 frames per second.
Integration Time = (524 + 1) * 65.20
μ
s = 34.23ms.
2.1.8 SFCM Integration Time Control
The Integration Time for the SFCM is defined by the in-
tegration time register (
Table 37 on page 39
through
Ta-
ble 39 on page 40
) and can be expressed as:
Integration Time = sint
d
* 16 * MCLK
period
where sint
d
is a number. Therefore, the user can adjust
integration time in steps of 16 MCLK periods.
2.2 Analog Signal Processing Chain Overview
The SCM20014’s analog signal processing (ASP) chain
incorporates Correlated Double Sampling (CDS),
Frame Rate Clamp (FRC), two Digitally Programmable
Gain Amplifiers (DPGA), Offset Correction (DOVA), and
a 10-bit Analog to Digital Converter (ADC).
2.2.1 Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of a ca-
pacitive node results in a reset noise which is equal to
kTC; C being the capacitance of the node, T the temper-
ature and k the Boltzmann constant. A common way of
eliminating this noise source in all image sensors is to
use Correlated Double Sampling. The output signal is
sampled twice, once for its reset (reference) level and
once for the actual video signal. These values are sam-
pled and held while a difference amplifier subtracts the
reference level from the signal output. Double sampling
of the signal eliminates correlated noise sources.
Figure 9. Conceptual block diagram of CDS
implementation.
2.2.2 Frame Rate Clamp (FRC)
The FRC (
Figure 10
) is designed to provide a feed for-
ward dark level subtract reference level measurement.
In the automatic FRC mode, the optical black level ref-
erence is re-established each time the image sensor
begins a new frame. The SCM20014 uses optical black
(dark) pixels to aid in establishing this reference.
On the SCM20014, dark pixel input signals should be
sampled for a minimum of 137
μ
s to allow the two 0.1
μ
F
capacitors at the CLRCA and CLRCB pins sufficient
time to charge for 10-bit accuracy. This guarantees that
the FRC’s “droop” will be maintained at <750
μ
V
,
thus
assuring the specified ADC 10-bit accuracy at +0.5
LSB. Therefore, at maximum operational frequency
(13.5 MHz), the imager would require 6 frames to estab-
lish the dark pixel reference for subsequent active pixel
processing. The dark pixel sample period is automati-
cally controlled internally and it is set to skip the first 2
dark rows and then sample the next dark row. When
“dark clamping” is active, each dark pixel is processed
and held to establish pixel reference level at the CLRCA
and CLRCB pins. During this period, the FRC’s differen-
tial outputs (V+ and V- on the Diff Amp,
Figure 10
) are
clamped to V
cm
. Together, these actions help to elimi-
nate the dark level offset, simultaneously establishing
the desired zero code at the ADC output.
Care should be exercised in choosing the capacitors for
the CLRCA, B pins to reflect different frame rates.
AMP
S/H1
S/H2
CDSP1
CDSP2
AVIN
V+
V-
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