參數(shù)資料
型號(hào)： SC16IS741IPW
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述： 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝： 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁(yè)數(shù)： 40/52頁(yè)
文件大?。?/td> 382K
代理商： SC16IS741IPW
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
40 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
14. Dynamic characteristics
[1]
A detailed description of the I
2
C-bus specification, with applications, is given in user manual UM10204:
“I
2
C-bus specification and user
manual”
. This may be found at
www.nxp.com/acrobat_download/usermanuals/UM10204.pdf
.
[2]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
[3]
2 XTAL1 clocks or 3
μ
s, whichever is less.
[4]
The device will not acknowledge if an I
2
C-bus transaction occurs during the ‘SCL delay time after reset’.
Table 33.
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
= 2.5 V
±
0.2 V, T
amb
=
40
°
C to +85
°
C; or V
DD
= 3.3 V
±
0.3 V, T
amb
=
40
°
C to +95
°
C; and refer to V
IL
and V
IH
with
an input voltage of V
SS
to V
DD
. All output load = 25 pF, except SDA output load = 400 pF.
Symbol
Parameter
Conditions
I
2
C-bus timing specifications
[1]
Standard mode
I
2
C-bus
Min
0
4.7
Fast mode
I
2
C-bus
Min
0
1.3
Unit
Max
100
-
Max
400
-
f
SCL
t
BUF
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
[2]
kHz
μ
s
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
4.0
4.7
4.7
0
-
-
-
-
-
-
0.6
0.6
0.6
0
-
-
-
-
-
-
μ
s
μ
s
μ
s
ns
μ
s
ns
0.6
0.6
0.6
0.6
SCL LOW to
data out valid
t
SU;DAT
t
LOW
t
HIGH
t
f
t
r
t
SP
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
modem interrupt valid delay time
modem interrupt clear delay time
receive interrupt valid delay time
receive interrupt clear delay time
transmit interrupt clear delay time
SCL delay time after reset
delay time from SCL to address
delay time from SDA to address
delay time from address to SCL
delay time from address to SDA
reset pulse width
250
4.7
4.0
-
-
-
-
-
-
150
1.3
0.6
-
-
-
-
-
-
ns
μ
s
μ
s
ns
ns
ns
300
1000
50
300
300
50
t
d(int_v)modem
t
d(int_clr)modem
t
d(int_v)rx
t
d(int_clr)rx
t
d(int_clr)tx
t
d(rst-SCL)
t
d(SCL-A)
t
d(SDA-A)
t
d(A-SCL)
t
d(A-SDA)
t
w(rst)
0.2
0.2
0.2
0.2
1.0
3
-
-
-
-
3
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.5
3
-
-
-
-
3
-
-
-
-
-
-
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
ns
μ
s
[3][4]
30
30
30
30
-
30
30
30
30
-
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