參數(shù)資料
型號: SC16IS741IPW
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述: 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁數(shù): 35/52頁
文件大?。?/td> 382K
代理商: SC16IS741IPW
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
35 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
10.3 Addressing
Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The first byte after the START condition carries the address of
the slave device and the read/write bit.
Table 28
shows how the SC16IS741’s address can
be selected by using A1 and A0 pins. For example, if these 2 pins are connected to V
DD
,
then the SC16IS741’s address is set to 0x90, and the master communicates with it
through this address.
Table 28.
A1
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
[1]
X = logic 0 for write cycle; X = logic 1 for read cycle.
[2]
Consult
Figure 23
and
Figure 24
if A1 or A0 is connected to SCL or SDA.
10.4 Use of subaddresses
When a master communicates with the SC16IS741 it must send a subaddress in the byte
following the slave address byte. This subaddress is the internal address of the word the
master wants to access for a single byte transfer, or the beginning of a sequence of
locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device
address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus
it must be followed by an acknowledge.
Table 29
shows the breakdown of the subaddress (register address) byte. Bit 0 is not
used, bits [2:1] are both set to zeroes, bits [6:3] are used to select one of the device’s
internal registers, and bit 7 is not used.
A register write cycle is shown in
Figure 18
. The START is followed by a slave address
byte with the direction bit set to ‘write’, a subaddress byte, a number of data bytes, and a
STOP signal. The subaddress indicates which register the master wants to access, and
the data bytes which follow will be written one after the other to the subaddress location.
SC16IS741 address map
A0
V
DD
V
SS
SCL
SDA
V
DD
V
SS
SCL
SDA
V
DD
V
SS
SCL
SDA
V
DD
V
SS
SCL
SDA
SC16IS741 I
2
C addresses (hex)
[1][2]
0x90 (1001 000X)
0x92 (1001 001X)
0x94 (1001 010X)
0x96 (1001 011X)
0x98 (1001 100X)
0x9A (1001 101X)
0x9C (1001 110X)
0x9E (1001 111X)
0xA0 (1010 000X)
0xA2 (1010 001X)
0xA4 (1010 010X)
0xA6 (1010 011X)
0xA8 (1010 100X)
0xAA (1010 101X)
0xAC (1010 110X)
0xAE (1010 111X)
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