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參數(shù)資料
| 型號(hào)： | SC16IS741IPW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
| 中文描述： | 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 382K |
| 代理商： | SC16IS741IPW |
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SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
22 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.5 Line Status Register (LSR)
Table 16
shows the Line Status Register bit settings.
Table 16.
Bit
7
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Line Status Register bits description
Symbol
Description
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = transmit hold register is not empty
logic 1 = transmit hold register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
LSR[4]
break interrupt
logic 0 = no break condition (normal default condition)
logic 1 = a break condition occurred and associated character is 0x00, that
is, RX was LOW for one character time frame
LSR[3]
framing error
logic 0 = no framing error in data being read from RX FIFO (normal default
condition).
logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit
LSR[2]
parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
LSR[1]
overrun error
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
LSR[0]
data in receiver
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
6
5
4
3
2
1
0
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| SC16IS741IPW,118 | 功能描述:UART 接口集成電路 SINGLE UART W/ 12C-BUS/SPI INTERFC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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| SC16IS74Q900 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs |
| SC16IS750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
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