參數(shù)資料
型號: SC16IS741IPW
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述: 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁數(shù): 25/52頁
文件大?。?/td> 382K
代理商: SC16IS741IPW
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
25 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation.
Table 19
shows the Interrupt Enable Register bit settings.
Table 19.
Bit
7
[1]
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
Interrupt Enable Register bits description
Symbol
Description
IER[7]
[1]
CTS interrupt enable
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
IER[6]
[1]
RTS interrupt enable
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
IER[5]
[1]
Xoff interrupt
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
IER[4]
[1]
Sleep mode
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
Section 7.6 “Sleep mode”
for details.
IER[3]
reserved
IER[2]
Receive Line Status interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
IER[1]
Transmit Holding Register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
IER[0]
Receive Holding Register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
6
5
4
3
2
1
0
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