參數(shù)資料
型號: SC16C2552BIA44
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs
封裝: SC16C2552BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 49, 2004,;SC16C2552BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html
文件頁數(shù): 21/38頁
文件大?。?/td> 179K
代理商: SC16C2552BIA44
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
21 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.9 Scratchpad Register (SPR)
The SC16C2552B provides a temporary data register to store 8 bits of user information.
7.10 Alternate Function Register (AFR)
This is a read/write register used to select specific modes of MF operation and to allow
both UART register’s sets to be written concurrently.
Table 19.
Bit
7:3
2:1
Alternate Function Register bit description
Symbol
Description
AFR[7:3]
Not used. All are initialized to logic 0.
AFR[2:1]
Selects a signal function for output on the MFA, MFB pins. These signal
functions are described as: OP2 (interrupt enable), BAUDOUT, or RXRDY.
Only one signal function can be selected at a time. See
Table 20
.
AFR[0]
When this bit is set, CPU can write concurrently to the same register in both
UARTs. This function is intended to reduce the dual UART initialization time.
It can be used by CPU when both channels are initialized to the same state.
The external CPU can set or clear this bit by accessing either register set.
When this bit is set, the Channel Select pin, CHSEL, still selects the channel
to be accessed during read operation. Setting or clearing this bit has no
effect on read operations. The user should ensure that LCR[7] of both
channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
logic 0 = no concurrent write (normal default condition)
logic 1 = register set A and B are written concurrently with a single external
CPU I/O write operation.
0
Table 20.
AFR[2]
0
0
1
1
MFA, MFB function selection
AFR[1]
0
1
0
1
MF function
OP2
BAUDOUT
RXRDY
reserved
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