參數(shù)資料
型號: SC16C2552BIA44
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs
封裝: SC16C2552BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 49, 2004,;SC16C2552BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html
文件頁數(shù): 4/38頁
文件大小: 179K
代理商: SC16C2552BIA44
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
4 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
D0
D1
D2
D3
D4
D5
D6
D7
DSRA
DSRB
2
3
4
5
6
7
8
9
41
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
Data bus (bidirectional).
These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU.
Data Set Ready A, B (active LOW).
These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates the modem or data set is powered-on
and is ready for data exchange with the UART.
Data Terminal Ready A, B (active LOW).
These outputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that the SC16C2552B is
powered-on and ready. This pin can be controlled via the modem control register. Writing a
logic 1 to MCR[0] will set the DTRn output to logic 0, enabling the modem. This pin will be a
logic 1 after writing a logic 0 to MCR[0], or after a reset.
Signal and power ground.
Interrupt A, B (active HIGH).
This function is associated with individual channel interrupts.
Interrupts are enabled in the Interrupt Enable Register (IER). Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or when a modem
status flag is detected.
Read strobe (active LOW).
A logic 0 transition on this pin will load the contents of an
internal register defined by address bits A[2:0] onto the SC16C2552B data bus (D[7:0]) for
access by external CPU.
Write strobe (active LOW).
A logic 0 transition on this pin will transfer the contents of the
data bus (D[7:0]) from the external CPU to an internal register that is defined by address bits
A[2:0].
Multi-function A, B.
This function is associated with an individual channel function, A or B.
User programmable bits 2:1 of the Alternate Function Register (AFR) selects a signal
function or output on these pins. OP2 (interrupt enable), BAUDOUT, and RXRDY are signal
functions that may be selected by the AFR. These signal functions are described as follows:
OP2.
When OP2 is selected, the MFn pin is a logic 0 when MCR[3] is set to a logic 1.
A logic 1 is the default signal condition that is available following a master reset or
power-up.
BAUDOUT.
When BAUDOUT function is selected, the 16
×
baud rate clock output is
available at this pin.
RXRDY.
RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive
data FIFOs. A logic 0 indicates there is receive data to read/unload, i.e., receive ready
status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not been
reached. This signal can also be used for single mode transfers (DMA mode 0).
Reset (active HIGH).
A logic 1 on this pin will reset the internal registers and all the outputs.
The UART transmitter output and the receiver input will be disabled during reset time. See
Section 7.11 “SC16C2552B external reset condition”
for initialization details.
Ring Indicator A, B (active LOW).
These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates the modem has received a ringing
signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt
if modem status interrupt is enabled.
DTRA
DTRB
37
27
O
O
GND
INTA
INTB
12, 22
34
17
I
O
O
IOR
24
I
IOW
20
I
MFA
MFB
35
19
O
O
RESET
21
I
RIA
RIB
43
31
I
I
Table 2.
Symbol
Pin description
…continued
Pin
Type
Description
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