參數(shù)資料
型號(hào)： SC16C2552BIA44
廠商： NXP Semiconductors N.V.
元件分類： 收發(fā)器
英文描述： 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs
封裝： SC16C2552BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 49, 2004,;SC16C2552BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html
文件頁數(shù)： 11/38頁
文件大小： 179K
代理商： SC16C2552BIA44
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
11 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.
Register descriptions
Table 6
details the assigned bit functions for the SC16C2552B internal registers. The
assigned bit functions are further defined in
Section 7.1
through
Section 7.11
.
[1]
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2]
The ‘General register set’ registers are accessible only when CS is a logic 0 and LCR[7] is logic 0.
[3]
The Baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 1.
Set A is accessible when CHSEL is a logic 1, and Set B is accessible when CHSEL is a logic 0.
Table 6.
A2
General register set
[2]
0
0
0
0
0
0
0
0
1
SC16C2552B internal registers
A0
Register Default
[1]
A1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RHR
THR
IER
XX
XX
00
bit 7
bit 7
0
bit 6
bit 6
0
bit 5
bit 5
0
bit 4
bit 4
0
bit 3
bit 3
modem
status
interrupt
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
bit 1
bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
bit 0
bit 0
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
0
0
DMA
mode
select
INT
priority
bit 2
parity
enable
FIFOs
enable
0
1
0
ISR
01
0
0
INT
status
0
1
1
LCR
00
divisor
latch
enable
0
set break set parity even
parity
word
length
bit 0
DTR
1
0
0
MCR
00
0
0
loopback OP2
output
control
framing
error
OP1
1
0
1
LSR
60
FIFO
data
error
CD
bit 7
THR and
TSR
empty
RI
bit 6
THR
empty
break
interrupt
parity
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special register set
[3]
0
0
0
0
0
1
0
1
0
1
1
0
1
MSR
SPR
X0
FF
DSR
bit 5
CTS
bit 4
CD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
AFR
XX
XX
00
bit 7
bit 15
bit 7
bit 6
bit 14
bit 6
bit 5
bit 13
bit 5
bit 4
bit 12
bit 4
bit 3
bit 11
bit 3
bit 2
bit 10
bit 2
bit 1
bit 9
bit 1
bit 0
bit 8
bit 0
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