參數(shù)資料
型號: SAF82526
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 77/126頁
文件大小: 730K
代理商: SAF82526
Semiconductor Group
77
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following figure gives an example of an interrupt controlled reception sequence, supposed
that a long frame (66 bytes) followed by two short frames (6 bytes each) are received.
Figure 37
Interrupt Driven Reception Sequence Example
Serial
Interface
HSCX
CPU
Interface
ITD00251
RPF
RMC
RD
Bytes
32
32
RD
Bytes
RMC
RPF
RME
RMC
RMC
RME
RME
RMC
R
32
32
2
6
6
Receive Frame
Bytes)
R
R
R
. . .
. . .
...
...
...
R
R
1(66
DMA Mode
If the RFIFO contains 32 bytes, the HSCX autonomously requests a block data transfer by
DMA activating the DRQR line as long as the start of the 32nd read cycle. This forces the DMA
controller to continuously perform bus cycles till 32 bytes are transferred from the HSCX to the
system memory.
If the RFIFO contains less than 32 bytes (one short frame or the last part of a long frame) the
HSCX requests a block data transfer depending on the contents of the RFIFO according to the
following table:
RFIFO
Contents
(Bytes)
DMA
Request
(Bytes)
1, 2, 3
4 - 7
8 - 15
16 - 32
4
8
16
32
Note:
All available status informations after RME are summarized in
table 10.
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