參數(shù)資料
型號(hào)： SAF82526
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 69/126頁
文件大小： 730K
代理商： SAF82526
Semiconductor Group
69
SAB 82525
SAB 82526
SAF 82525
SAF 82526
7
Operational Description
7.1 RESET
The HSCX is forced into the reset state if a high signal is input to the RES pin for a minimum
period of 1.8
μ
s. During RESET, the HSCX is temporarily in the power-up mode, and a subset
of the registers is initialized with defined values.
After RESET, the HSCX is in power down mode, and the following registers contain defined
values:
Table 7
RESET Values
Register
RESET
Value
Meaning
CCR1
00
H
– power down mode
serial port configuration; pt-pt, NRZ coding, transmit data pins
are open drain outputs
– clock mode 0
CCR2
00
H
RTS pin normal function
– CTS and RFS interrupts disabled no data inversion
MODE
00
H
auto-mode
1 byte address field
external timer mode
– receivers inactive
RTS output controlled by HSCX, timer resolution:
k = 32.768, no testloop
STAR
48
H
XFIFO write enable
receive line inactive
no commands executing
ISTA
EXIR
00
H
– no interrupts masked
CMDR
00
H
00
H
no commands
XBCH
RBCH
– interrupt controlled data transfer (DMA disabled)
– full-duplex LAPB/LAPD operation of LAP controller
– carrier detect auto start of receiver disabled
XCCR
RCCR
00
H
1-bit time-slot
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