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參數(shù)資料
| 型號： | SAF82526 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Data Communications ICs |
| 中文描述： | 數(shù)據(jù)通信集成電路 |
| 文件頁數(shù)： | 65/126頁 |
| 文件大?。?/td> | 730K |
| 代理商： | SAF82526 |
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Semiconductor Group
65
SAB 82525
SAB 82526
SAF 82525
SAF 82526
This feature can be profitably used e.g. for:
user specific protocol variations
the application of character oriented protocols (e.g. BISYNC)
test purposes, line intentionally violation of HDLC protocol rules (e.g. wrong CRC)
FLAG insertion and deletion
CRC generation and checking
Bit-stuffing mechanism.
In order to enable fully transparent data transfer, RAC bit in MODE has to be reset and FF
H
has to be written to XAD1, XAD2 and RAH2.
Data transmission is always performed out of the transmit FIFO by directly shifting the contents
of the XFIFO via the serial transmit data pin (T
×
D). Transmission is initiated by setting
CMDR : XTF (08
H
); end of transmission is indicated by EXIR : EXE (40
H
).
In receive direction, the character currently assembled via the receive data line (R
×
D) is
available in the RAL1 register. Additionally, in extended transparent mode 1 (MODE: MDS1,
MDS0, ADM = 111), the received data is shifted into the RFIFO.
6
6.1 Fully Transparent Transmission and Reception
When programmed to the extended transparent mode via the MODE register (MDS1,
MDS0 = 11), each channel of the HSCX supports fully transparent data transmission and
reception without HDLC framing overhead, i.e. without
Special Functions
Character synchronization can be achieved either in
clock mode 1, with an external receive strobe input to A
×
CLK pin, or
clock mode 5, with a programmed time-slot and a frame synchronization signal input to
A
×
CLK.
Using clock mode 1 or 5 multiples of 8 bits received per time-slot.
6.2 Cyclic Transmission (Fully Transparent)
If the extended transparent mode is selected, the HSCX supports the continuous transmission
of the transmit FIFO’s contents.
After having written 1 to 32 bytes to the XFIFO, the command
XREP.XTF.XME
via the CMDR register (bit 7. . .0 = "00101010" = 2AH) forces the HSCX to repeatedly transmit
the data stored in the XFIFO via T
×
D pin.
The cyclic transmission continues until a reset command (CMDR : XRES) is issued, after
which continuous ’1’-s are transmitted.
Note:
In DMA-mode the command XREP, XTF has to be written to CMDR.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAF82526N | Data Communications ICs |
| SAB82525 | Data Communications ICs |
| SAB82525H | Data Communications ICs |
| SAF82532H-10 | ICs for Communications |
| SAB82532 | ICs for Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF82526HV2.1-HSCX-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SAF82526N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Data Communications ICs |
| SAF82526NV2.2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| SAF82526NV2.2XT | 制造商:Infineon Technologies AG 功能描述:Communication Controller 44-Pin PLCC T/R |
| SAF82532 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ICs for Communications |
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