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參數(shù)資料
| 型號： | SAF7847HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, SOT486-1, MS-026, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 71/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7847HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
71 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
7.2.3.4
Burst reads from external memory
The static memory control unit can support a maximum of four consecutive reads from
external reads. This feature supports burst mode ROM devices.
This feature increases the bandwidth for sequential reads compared to non-sequential
reads. The burst access requires the user to specify the access times in SMBWST2x; for
single reads, the access times are specified as wait-states in SMBWST1x.
The chip-select and output-enable lines are held during burst mode transfers.
It is also important to note that the burst transfers cannot cross quad boundaries. For
eight bits, this implies: ARM address[1:0] = 11, and for 16 bits: ARM address[2:1] = 11.
Example for a 16-bit wide external memory:
1. If start address is ARM address[2:1] = 01, this address starts as a slow read, and
hence the SMBWST1x value applies.
2. The next sequential address is ARM address[2:1] = 10 and 11. These addresses are
fast reads and hence the SMBWST2x value applies.
3. The final address before the burst transfer completes is ARM address[2:1] = 00. The
final read is slow (more wait-states apply), and the SMBWST1x value applies.
7.2.4
Write access to external memory
Writing to external memory requires a similar setup to that described for reading from
external memory.
The write-enable parameter needs to be programmed.
Writing to external memory can be extended by applying wait-states as described for
reading from external memory.
7.2.4.1
Write-enable programmable delay
This is the programmable delay between the asserted chip-select and the asserted
write-enable. A total of 15 cycles can be asserted. The wait-state values are programmed
in field WSTEN in register SMBCRx.
When no write-enable delay is programmed, the hardware introduces a default delay of
one clock cycle between active chip-select and asserting write control.
The write-enable delay programmed in WSTEN must be less than the wait-state
programmed in register SMBWST2x.
7.2.5
SMIU operation parameters to calculate latency
The delay through the logic to external memory are categorized in three sections:
Default hardware latency, with no software-programmable increase in delay
Software-programmable increase in latency delay
Standard delay through logic including pads
The following requirements must be taken into account when computing the overall
latency delay:
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
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