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參數(shù)資料
| 型號： | SAF7847HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, SOT486-1, MS-026, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 69/93頁 |
| 文件大小： | 396K |
| 代理商： | SAF7847HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
69 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
7.2.3
Read access to external memories
The sections below describe the step-by-step process required for setting up the static
memory interface unit registers prior to accessing the external memory.
7.2.3.1
Programming the external memory data widths
The bank configuration register SMBCRx (x = bank number, 0 or 1), is used to describe
the bus width. The SAF784x can only support an external data bus width of 16-bits. If,
during a data transfer requested by the internal ARM, the external data width is narrower
than the ARM bus data width, several interface bus cycles may be required to complete
the transfer. For example, if the external memory data bus is 16-bits wide, and a 32-bit
read is requested by the ARM, the AHB bus is stalled until the static memory interface unit
has fetched the two half words.
7.2.3.2
Wait-state generation
The wait-state assertion registers are SMBWST1Rx and SMBWST2Rx. Note that ‘x’
denotes the bank number (0 or 1).
The wait-state time is crucial, as the internal AHB bus cycles are scaled with respect to
the access times of the external memory. The highest number of wait-states that can be
asserted is 31 system clock cycles. The maximum AHB clock frequency for the SAF784x,
is 76 MHz.
Hence the maximum access time that can be supported for this implementation of
wait-state register is 13 ns
×
31 cycles. The minimum wait-state assertion time is when the
wait-state field in the register is 0 and the hardware asserts a wait time of 2
×
13 ns. This
is the fastest external memory access time.
This is an important parameter to consider when selecting the memory type to interface
with the static memory interface unit.
Each wait-state register has a particular importance for the following actions:
SMBWST1Rx when performing read transfers from external memory; SMBWST2Rx when
performing write transfers to external registers.
An example of the effect of wait-state assertion when reading from external memory is
shown in
Figure 38
.
7.2.3.3
Output-enable delay programming
The output enable can be programmed, at the time it needs to be active. This is typically
after the memory has been selected, by toggling the chip-select lines. The maximum
programmable delay between when the chip-select is active and when the output-enable
activates is 15 cycles. The output-enable delay value is programmed in field WSTOEN in
register SMBCRx.
This feature is intended for memory that may not be able to provide valid output
immediately after the chip-select lines are active. Note that the output-enable is
de-asserted at the same time as the chip-select lines at the end of a transfer.
Remark:
The output-enable delay programmed in WSTOEN must be less than the
programmed wait-state. Note that the external memory access times are determined by
the wait-states and not by the output-enable delay.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
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