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參數(shù)資料
| 型號： | SAF7847HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, SOT486-1, MS-026, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 37/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7847HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
37 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
6.5.7
Main data decoding
6.5.7.1
Data processing
The CD main data is de-interleaved and error-corrected according to the CD Red Book
(IEC 60908)CIRC decoding standards, and uses an internal SRAM as buffer and FIFO.
The C1 correction will correct up to two errors per EFM frame, and will flag all
uncorrectable frames as an erasure. The C2 error correction will correct up to two errors
or four erasures, and will also flag all uncorrectable frames as an erasure.
The decoding operation is controlled by register DecoMode. There are basically two
decode operating modes:
Flush mode: the de-interleaver tables are emptied, and all internal pointers are reset.
No data is written into the buffer, no corrections are done, and no data is output
Play mode: de-interleaver tables are filled, C1 or C2 corrections are done, and data is
output, when available
During Flush mode, no data is output from the device. During Play mode, data is output
via the I
2
S interface as soon as it is available in the internal FIFO.
Figure 19
shows the operation of the FIFO and corrections during CD playback.
De-interleaving of the data is done as required by the CD Red Book (IEC 60908)
specification. De-interleaving is performed by the SRAM FIFO address calculation
functions in the memory processor. Two corrections are done: C1 followed by C2.
6.5.7.2
Data Latency + FIFO operation
System data latency is a function of the minimum amount of data required in the FIFO to
perform the de-interleaving operation. The latency is quoted in the number of C1 frames
(24 bytes of user data). The latency of the CIRC decoder is 118 frames.
The FIFO filling is defined as this ‘data latency’ + the number of extra frames stored in the
FIFO. The filling of the FIFO must be maintained within certain limits. 118 frames is the
minimum required for de-interleaving, 128 is the physical maximum limit determined by
the used SRAM size. This results in a usable FIFO size of 11 frames. The FIFO filling can
be read back via register FIFOFill.
The FIFO filling must have a correct value. This can be achieved in two ways:
Fig 19. Data processing during CD mode
001aag323
'd'
de-interleave
data from
demodulator
to I
2
S
back end
C1
correction
C2
correction
FIFO
FIFO filling
'D'
de-interleave
delta
de-interleave
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
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