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參數(shù)資料
| 型號： | SAF7847HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, SOT486-1, MS-026, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 31/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7847HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
31 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
optional manual selection of the PLL state (in-lock, inner-lock, outer-lock, outer-lock
with only RL3 regulation).
optional pre-set of the PLL frequency to a certain value
Overriding the PLL state:
PLL state can be:
In-lock
Inner lock
Outer lock
Outer lock with only RL3 regulation
Hold
Normally, the PLL state is selected automatically by the lock detectors. However, the PLL
lock state can be overruled via register PLLLockAidControl. When Lock mode is left at ‘0’,
the user can still choose the PLL state, but hardware will overwrite this if the
hardware-selected PLL state is closer to locking the PLL.
[1]
During PLL hold, the PLL frequency will not change and the frequency preset may be used.
It is possible to pre-set the PLL frequency to a certain value by writing the integrator value
of the PLL to register PLLIntegrator. The relationship between the bit frequency, the
integrator value, and the sysclk frequency f
clk(sys)
is given by:
(2)
The real-time value of the PLL frequency can be read at the same address.
6.5.5.3
Limiting the PLL frequency range
The range over which the PLL can capture the input frequency can be limited. The
minimum and maximum PLL frequency can be set by bits MININTFREQ, and
MAXINTFREQ respectively in register PLLMinMaxBounds.
6.5.5.4
Run length 2 push-back detector
If this circuit is switched on, all run length one and two symbols (invalid run lengths) are
pushed back to run length 3. For RL2s, the circuit will determine the transition that was
most likely to be in error, and shift transition on that edge. This feature should always be
turned on, but can be deselected via register RL2PushBack.
Table 5.
Lock mode
0
1
1
1
1
1
x
PLL lock states
PLLLockControl
0 0000
0 0001
0 0110
0 0100
0 1000
1 0100
others
State
[1]
automatic lock behavior
force HF PLL into in-lock
force HF PLL into inner-lock aid
force HF PLL into outer-lock aid
force HF PLL into hold mode
force HF PLL into outer-lock aid with RL3 regulation only
reserved
f
clk bit
)
ch
PLLFreq 7:0
]
4
+
128
f
clk sys
)
×
Hz
(
)
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
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