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參數(shù)資料
| 型號： | SAF7847HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, SOT486-1, MS-026, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 30/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7847HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
30 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
f
1
: Integrator cross-over controlled via K
I
f
0
: PLL bandwidth controlled via K
P
f
2
: LPF bandwidth controlled via K
F
The three frequencies are programmable using register PLLBandWidth. The higher
bandwidths for use after a defect, are programmed in register PLLBandWidthHigh; see
Section “Defect detector” on page 26
.
When the PLL is in lock, the recovered PLL clock frequency equals the channel bit clock
frequency.
Detection of PLL lock:
The PLL locking state is determined by the distance between
detected syncs. This means that the sync detection is actually controlling the automatic
PLL locking.
The PLL switches from outer lock to inner lock when successive syncs are detected to be
588
±
25 channel bits apart. Internally this is also called a ‘winsync’ (sync falls in a wider
window). The number of missed winsyncs is kept in a 3-bit confidence counter, and the
PLL will go out of outer lock when seven consecutive out-of-window syncs are found.
The PLL switches from inner lock to in-lock when successive syncs are detected 588
±
1
channel bits apart. The number of consecutive missed syncs is kept in a bit counter, and
saturates on either 16 or 61, depending on the value of bit LOCK[16] or [61] in register
DemodControl. When the saturation level is reached, the PLL is set out-of-lock.
The PLL frequency (inner-) and phase (in-) lock status can be read out in register
PLLLockStatus.
PLL outer-lock aid:
The outer lock aid has no limitation on capture range, and will bring
the PLL within the range of the inner lock aid. The PLL will first regulate its frequency
based on detecting RL3s as the smallest possible RLs (fast-but-rough regulation), and
next on detecting RL11s as the largest possible RLs (slow but more accurate).
PLL inner-lock aid:
The inner-lock aid has a capture range of
±
4 %, and will bring the
PLL frequency to the phase-lock point. It will regulate the PLL frequency such that
588-bits are detected between two EFM-syncs.
Influencing PLL behavior:
Programmability and observer ability are built into the PLL
mainly for debugging purposes, and also to make difficult applications possible. The PLL
operation can be influenced in two ways:
Fig 17. PLL bode diagram
001aag321
loop gain
frequency
f
1
f
0
f
LPF
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| SB10100F | ISOLATION SCHOTTKY BARRIER RECTIFIERS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
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